ISQED 2019: Program
Revised Jan. 15. 2019


SESSION 1A

Wednesday March 6

Machine Learning in Conventional and Emerging Platforms

Chair: Prof. Ronald DeMara, University of Central Florida
Co-Chair: tbd, tbd

10:00AM
1A.1
kNN-CAM: A kNN-based Configurable Approximate Floating Point Multiplier for Energy-Area Minimization
Ming Yan1, Yuntao Song2, Yiyu Feng2, Ghasem Pasandi3, Massoud Pedram2, Shahin Nazarian2
1University of Southern California, Ming Hsieh Department of Electrical Engineering, 2USC, 3University of Southern California

10:20AM
1A.2
Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Efficiency, and Power-Intermittency Resilience
Arman Roohi1, Shaahin Angizi2, Deliang Fan3, Ronald F DeMara3
1Computer Systems and Architecture Laboratory, Department of EECS, University of Central Florida, 2Department of Electrical and Computer Engineering, University of Central Florida, 3University of Central Florida

10:40AM
1A.3
Towards Collaborative Intelligence Friendly Architectures for Deep Learning
Amir Erfan Eshratifar1, Amirhossein Esmaili1, Massoud Pedram2
1University of Southern California, 2USC

11:00AM
1A.4
A General Framework to Map Neural Networks onto Neuromorphic Processor
haowen fang1, Amar Shrestha1, Ziyi Zhao1, Yanzhi Wang2, Qinru Qiu1
1syracuse university, 2University of Southern California


SESSION 1B

Wednesday March 6

Modern High-Level and Logic Synthesis

Chair: tbd, tbd
Co-Chair: tbd, tbd

10:00AM
1B.1
Approximate Logic Synthesis: A Reinforcement Learning-Based Technology Mapping Approach
Ghasem Pasandi1, Massoud Pedram2, Shahin Nazarian2
1University of Southern California, 2USC

10:20AM
1B.2
Fast Mapping-Based High-Level Synthesis of Pipelined Circuits
Chaofan Li1, Sachin S. Sapatnekar2, Jiang Hu3
1Synopsys Inc., 2University of Minnesota, 3Texas A&M University

10:40AM
1B.3
Characterization of Fast, Accurate Leakage Power Models for IEEE P2416
Barkha Gupta and W. Rhett Davis
North Carolina State University

11:00AM
1B.4
Synthesis of Algorithm Considering Communication Structure of Distributed/Parallel Computing
Yukio Miyasaka1, Ashish Mittal2, Masahiro Fujita1
1University of Tokyo, 2Indian Institute of Technology Bombay


SESSION 1C

Wednesday March 6

Emerging Memory and Spintronics Technologies for Future Energy Efficient Applications

Chair: tbd, tbd
Co-Chair: tbd, tbd

10:00AM
1C.1
Using Spin-Hall MTJs to Build an Energy-Efficient In-memory Computation Platform
Masoud Zabihi, Zhengyang Zhao, Mahendra DC, Zamshed Chowdhury, Mike Resch, Thomas Peterson, Ulya R. Karpuzu, Jian-Ping Wang, Sachin S. Sapatnekar
University of Minnesota

10:20AM
1C.2
Low Restoration-Energy Differential Spin Hall Effect MRAM for High-Speed Nonvolatile SRAM Application
SONAL SHREYA1 and Brajesh Kumar Kaushik2
1Indian Institute of Technology Roorkee, 2I.I.T-Roorkee

10:40AM
1C.3
A Multi-Driver Write Scheme for Reliable and Energy Efficient 1S1R ReRAM Crossbar Arrays
Sherif Amer1 and Garrett Rose2
1University of Tennessee, 2The University of Tennessee

11:00AM
1C.4
Application of Probabilistic Spin Logic (PSL) in detecting satisfiability of a Boolean function
Vaibhav Agarwal1 and Sneh Saurabh2
1IIITD, 2Indraprastha Institute of Information Technology


SESSION 2A

Wednesday March 6

Advances in Simulation, Design Optimization and Debug

Chair: tbd, tbd
Co-Chair: tbd, tbd

3:45PM
2A.1
A Compact Model of Negative Bias Temperature Instability Suitable for Gate-Level Circuit Simulation
Xu Liu1, Xing Zhou1, Ulf Schlichtmann2, Alessandro Bernardini2
1Nanyang Technological University, 2Technical University of Munich

4:05PM
2A.2
An Automated Design Flow for Synthesis of Optimal Switching Power Supply
Pradeep Chawda1, Anupriya Prasad2, Kunjal Rathod3, Kritika Solanki4
1Texas Instruments, 2IEEE Member, 3Senior Member, IEEE, 4Student Member, IEEE

4:25PM
2A.3
Robust Transistor Sizing for Improved Performances in Digital Circuits using Optimization Algorithms
Prateek Gupta1, Harshini Mandadapu2, Shirisha Gourishetty2, Zia Abbas2
1IIIT H, 2International Institute of Information Technology, Hyderabad

4:45PM
2A.4
Error Resilient Reorder Buffer Design for Network-On-Chip
Zheng Xu1 and Jacob Abraham2
1ARM, Inc., 2University of Texas

5:05PM
2A.5
Simulation Based Assessment of SRAM Data Retention Voltage
Zhipeng Dong, Xi Cao, Vivek Joshi, Muhammed Ahosan Ul Karim, Torsten Klick, Joerg Schmid
GLOBALFOUNDRIES


SESSION 2B

Wednesday March 6

System Level Tools, Flows, Methods

Chair: Hana Kubatova (Tentative), CTU in Prague
Co-Chair: n/a, n/a

3:45PM
2B.1
Evaluating Design Space Subsetting for Multi-Objective Optimization in Configurable Systems
Mohamad Hammam Alsafrjalani1, Tosiron Adegbija2, Lokesh Ramamoorthi1
1University of Miami, 2University of Arizona

4:05PM
2B.2
A Scalable Image/Video Processing Platform with Open Source Design and Verification Environment
Xiaokun Yang1, Yunxiang Zhang1, Lei Wu2
1University of Houston Clear Lake, 2Auburn University at Montgomery

4:25PM
2B.3
Power-aware IoT based Smart Health Monitoring using Wireless Body Area Network
Jitumani Sarma1, Akash Katiyar2, Rakesh Biswas2, Hemanta Kumar Mondal2
1Indian Institute of Information Technology, Guwahati, 2Indian Institute of Information Technology Guwahati, India

4:45PM
2B.4
A Comprehensive Evaluation of Power Delivery Schemes for Modern Microprocessors
Jawad Haj-Yahya1, Efraim Rotem2, Avi Mendelson3, Anupam Chattopadhyay4
1School of Computer Science and Engineering, Nanyang Technological University, 2CPU Architect, Intel, Israel, 3EE and CS Technion, Israel, 4Nanyang Technological University

5:05PM
2B.5
State Preserving Dynamic DRAM Bank Re-Configurations for Enhanced Power Efficiency
Kaustav Goswami1, Hemanta Kumar Mondal1, Shirshendu Das2, Dip Sankar Banerjee2
1Indian Institute of Information Technology Guwahati India, 2Indian Institute of Information Technology Guwahati


SESSION 2C

Wednesday March 6

High Performance Application Specific Architecture

Chair: Shomit Das, AMD Research
Co-Chair: Aswin Mehta, Texas Instruments

3:45PM
2C.1
Deterministic Stochastic Computation Using Parallel Datapaths
Alexander Groszewski and Travis Lenz
University of Texas at Austin

4:05PM
2C.2
MAPIM: Mat Parallelism for High Performance Processing in Non-volatile Memory Architecture
Joonseop Sim1, Minsu Kim2, Yeseong Kim3, Saransh Gupta4, Behnam Khaleghi4, Tajana Rosing5
1University of California, Sandiego, 2University of Minnesota, 3University of California San Diego, 4University of California, San Diego, 5UCSD

4:25PM
2C.3
Amoeba-Inspired Stochastic Hardware SAT Solver
Kazuaki Hara1, Naoki Takeuchi2, Masashi Aono3, Yuko Hara-Azumi1
1Tokyo Institute of Technology, 2Yokohama National University, 3Keio University

4:45PM
2C.4
Accelerating Deterministic Bit-Stream Computing with Resolution Splitting
M. Hassan Najafi1, Sayed Abdolrasoul Faraji2, Bingzhe Li2, David Lilja2, Kia Bazargan3
1University of Louisiana at Lafayette, 2University of Minnesota, Twin Cities, 3University of Minnesota

5:05PM
2C.5
High-Performance NoCs employing the DSP48E1 blocks of the Xilinx FPGAs
Prabhu Prasad B M1, Khyamling parane2, Basavaraj Talawar3
1National Institute of Technology Karnataka, Surathkal, 2National Institute of Technology Karnataka, 3CSE, NITK, Surathkal


SESSION 3A

Thursday March 7

Deep Learning Circuits and Architectures

Chair: tbd, tbd
Co-Chair: tbd, tbd

10:00AM
3A.1
MReC: A Multilayer Photonic Reservoir Computing Architecture
Dharanidhar Dhang, Syed Ali Hasnain, Rabi Mahapatra
Texas A&M University

10:20AM
3A.2
Dynamic Reconfiguration of CNNs for Input-Dependent Approximation
Maedeh Hemmat1 and Azadeh Davoodi2
1University of Wisconsin-Madison, 2University of Wisconsin, Madison

10:40AM
3A.3
An Application Specific Processor Architecture with 3D Inetegration for Recurrent Neural Networks
Sumon Dey and Paul D. Franzon
North Carolina State University

11:00AM
3A.4
Task-Based Processing and Modulation Architecture for Lifelong Learning
Anurag Daram1, Dhireesha Kudithipudi1, Angel Yanguas-Gil2
1Rochester Institute of Technology, 2Argonne National Laboratory,Lemont


SESSION 3B

Thursday March 7

Physical Design Optimization

Chair: tbd, tbd
Co-Chair: tbd, tbd

10:00AM
3B.1
Drive-Strength Selection for Synthesis of Leakage-Dominant Circuits
Mahfuzul Islam1, Shinichi Nishizawa2, Yusuke Matsui3, Yoshinobu Ichida3
1Kyoto University, 2Saitama University, 3ROHM Semiconductor

10:20AM
3B.2
Estimating Pareto Optimum Fronts to Determine Knob Settings in Electronic Design Automation Tools
Billy Huggins, W. Rhett Davis, Paul Franzon
North Carolina State University

10:40AM
3B.3
An Artificial Intelligence Approach to EDA Software Testing: Application to Net Delay Algorithms in FPGAs
Madhu Raman, Nizar Abdallah, Julien Dunoyer
Microsemi

11:00AM
3B.4
Impact of Double-Row Height Standard Cells on Placement and Routing
Rung-Bin Lin and Yu-Xiang Chiang
Yuan Ze University


SESSION 3C

Thursday March 7

Co-Optimization of Device Performance and Design Reliability from State-of-the-art FinFET to Quantum Technologies

Chair: tbd, tbd
Co-Chair: tbd, tbd

10:00AM
3C.1
Semi-formal Verification Framework and Benchmark for Single Flux Quantum Technology
Alvin Wong1, Kevin Su1, Hang Sun1, Arash Fayyazi1, Massoud Pedram2, Shahin Nazarian1
1University of Southern California, 2USC

10:20AM
3C.2
Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications
Ya-Chi Huang, Meng-Hsueh Chiang, Shui-Jinn Wang
National Cheng Kung University

10:40AM
3C.3
Impact of Self-heating on Performance and Reliability in FinFET and GAAFET Designs
Vidya Chhabria1 and Sachin S. Sapatnekar2
1University of Minnesota, Twin Cities, 2University of Minnesota

11:00AM
3C.4
Device Designs and Analog Performance Analysis for Negative-Capacitance Vertical-Tunnel FET
Hung-Han Lin and Vita Pi-Ho Hu
National Central University


SESSION 4A

Thursday March 7

Artificial Intelligence for Efficient Application Specific Hardware

Chair: Dr. Amey Kulkarni, Velodyne LiDAR
Co-Chair: Dr. Abhilash Goyal, Velodyne LiDAR

11:40AM
4A.1
Behavioral Modeling of Tunable I/O Drivers with Pre-emphasis Using Neural Networks
Huan Yu1, Jaemin Shin2, Tim Michalka2, Mourad Larbi1, Madhavan Swaminathan1
1Georgia Institute of Technology, 2Qualcomm Technologies, Inc.

12:00PM
4A.2
Small Memory Footprint Neural Network Accelerators
Kenshu Seto1, Hamid Nejatollahi2, Jiyoung An3, Sujin Kang4, Nikil Dutt2
1Tokyo City University, 2University of California, Irvine, 3Kyung Hee University, 4Hanyang University

12:20PM
4A.3
Minimizing Classification Energy of Binarized Neural Network Inference for Wearable Devices
Morteza Hosseini1, Hirenkumar Paneliya2, Utteja Panchakshara Kallakuri Niyogi3, mohit khatwani3, Tinoosh Mohsenin2
1author, 2University of Maryland Baltimore County, 3University of Maryland, Baltimore County

12:40PM
4A.4
Exploiting Energy-Accuracy Trade-off through Contextual Awareness in Multi-Stage Convolutional Neural Networks
Katayoun neshatpour, Farnaz Behnia, Houman Homayoun, Avesta Sasan
George Mason University


SESSION 4B

Thursday March 7

Verification, ATPG and Failure Analysis

Chair: Vinod Vishwanath, Real Intent, Inc.
Co-Chair: Sreejit Chakravarty, Intel Corporation

11:40AM
4B.1
Assertion Coverage Aware Trace Signal Selection in Post-Silicon Validation
Xiaobang Liu and Ranga Vemuri
University of Cincinnati

12:00PM
4B.2
A Communication-Centric Observability Selection for Post-Silicon System-on-Chip Integration Debug
Yuting Cao1, Hao Zheng1, Sandip Ray2
1University of South Florida, 2University of Florida

12:20PM
4B.2
Automatic Test Pattern Generation for Double Stuck-at Faults Based on Test Patterns of Single Faults
Peikun Wang1, Amir Masoud Gharehbaghi2, Masahiro Fujita1
1University of Tokyo, 2The University of Tokyo

12:40PM
4B.2
Deep Learning-Based Wafer-Map Failure Pattern Recognition Framework
Tsutomu Ishida, Izumi Nitta, Daisuke Fukuda, Yuzi Kanazawa
Fujitsu Laboratories Ltd.


SESSION 4C

Thursday March 7

Innovations In Classic Hardware Security Problems

Chair: Lin Yuan, n/a
Co-Chair: Anupam Chattopadhyay, Nanyang Technological University

11:40AM
4C.1
PUF-PassSE: A PUF based Password Strength Enhancer for IoT Applications
Qian Wang1, Mingze Gao2, Gang Qu3
1University of Maryland, 2University of Maryland, College Park, 3Univ. of Maryland, College Park

12:00PM
4C.2
On SAT-Based Attacks On Encrypted Sequential Logic Circuits
Yasaswy Kasarabada, Suyuan Chen, Ranga Vemuri
University of Cincinnati

12:20PM
4C.3
A Darwinian Genetic Algorithm for State Encoding Based Finite State Machine Watermarking
Matthew Lewandowski and Srinivas Katkoori
University of South Florida

12:40PM
4C.4
Lightweight Secure-Boot Architecture for RISC-V System-on-Chip
Anupam Chattopadhyay
Nanyang Technological University


SESSION 5A

Thursday March 7

Closing the SOC Verification Gap with Static Analysis

Chair: Vinod Vishwanath, Real Intent, Inc.
Co-Chair: tbd, tbd


SESSION 5B

Thursday March 7

3D Integration & Advanced Packaging

Chair: tbd, tbd
Co-Chair: tbd, tbd

3:40PM
5B.1
A Non-Slicing 3-D Floorplan Representation for Monolithic 3-D IC Design
Shantonu Das and Dae Hyun Kim
Washington State University

4:00PM
5B.2
Routing Complexity Minimization of Monolithic Three-Dimensional Integrated Circuits
Sheng-En(David) Lin and Dae Hyun Kim
Washington State University