Chair: Prof. Ronald DeMara, University of Central Florida
Co-Chair: Dr. Sicheng Li, HPE

10:00AM
1A.1
kNN-CAM: A k-Nearest Neighbors-based Configurable Approximate Floating Point Multiplier
Ming Yan¹, Yuntao Song², Yiyu Feng², Ghasem Pasandi³, Massoud Pedram², Shahin Nazarian^2
1University of Southern California, Ming Hsieh Department of Electrical Engineering, ²USC, ³University of Southern California

10:20AM
1A.2
Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Efficiency, and Power-Intermittency Resilience
Arman Roohi¹, Shaahin Angizi², Deliang Fan³, Ronald F DeMara^3
1Computer Systems and Architecture Laboratory, Department of EECS, University of Central Florida, ²Department of Electrical and Computer Engineering, University of Central Florida, ³University of Central Florida

10:40AM
1A.3
Towards Collaborative Intelligence Friendly Architectures for Deep Learning
Amir Erfan Eshratifar¹, Amirhossein Esmaili¹, Massoud Pedram^2
1University of Southern California, ²USC

11:00AM
1A.4
A General Framework to Map Neural Networks onto Neuromorphic Processor
haowen fang¹, Amar Shrestha¹, Ziyi Zhao¹, Yanzhi Wang², Qinru Qiu^1
1syracuse university, ²University of Southern California

Chair: Srinivas Katkoori, University of South Florida
Co-Chair: Srini Krishnamoorthy, Apple

10:00AM
1B.1
Approximate Logic Synthesis: A Reinforcement Learning-Based Technology Mapping Approach
Ghasem Pasandi¹, Shahin Nazarian², Massoud Pedram^2
1University of Southern California, ²USC

10:20AM
1B.2
Fast Mapping-Based High-Level Synthesis of Pipelined Circuits
Chaofan Li¹, Sachin S. Sapatnekar², Jiang Hu^3
1Synopsys Inc., ²University of Minnesota, ³Texas A&M University

10:40AM
1B.3
Characterization of Fast, Accurate Leakage Power Models for IEEE P2416
Barkha Gupta and W. Rhett Davis
North Carolina State University

11:00AM
1B.4
Synthesis of Algorithm Considering Communication Structure of Distributed/Parallel Computing
Yukio Miyasaka¹, Ashish Mittal², Masahiro Fujita^1
1University of Tokyo, ²Indian Institute of Technology Bombay

Chair: Aswin Mehta, Texas Instruments
Co-Chair: Prof. Vita Hu, National Central University, Taiwan

10:00AM
1C.1
Using Spin-Hall MTJs to Build an Energy-Efficient In-memory Computation Platform
Masoud Zabihi, Zhengyang Zhao, Mahendra DC, Zamshed I. Chowdhury, Salonik Resch, Thomas Peterson, Ulya R. Karpuzcu, Jian-Ping Wang, Sachin S. Sapatnekar
University of Minnesota

10:20AM
1C.2
Low Restoration-Energy Differential Spin Hall Effect MRAM for High-Speed Nonvolatile SRAM Application
Sonal Shreya and Brajesh Kumar Kaushik
Indian Institute of Technology Roorkee

10:40AM
1C.3
A Multi-Driver Write Scheme for Reliable and Energy Efficient 1S1R ReRAM Crossbar Arrays
Sherif Amer¹ and Garrett Rose^2
1University of Tennessee, ²The University of Tennessee

11:00AM
1C.4
Application of Probabilistic Spin Logic (PSL) in detecting satisfiability of a Boolean function
Vaibhav Agarwal¹ and Sneh Saurabh^2
1IIITD, ²Indraprastha Institute of Information Technology

Chair: Srini Krishnamoorthy, Apple
Co-Chair: Srinivas Katkoori, University of South Florida

3:45PM
2A.1
A Compact Model of Negative Bias Temperature Instability Suitable for Gate-Level Circuit Simulation
Xu Liu¹, Alessandro Bernardini², Ulf Schlichtmann², Xing Zhou^1
1Nanyang Technological University, ²Technical University of Munich

4:05PM
2A.2
An Automated Design Flow for Synthesis of Optimal Switching Power Supply
Pradeep Chawda¹, Anupriya Prasad¹, Kunjal Rathod², Kritika Solanki^3
1Texas Instruments, ²VMWare, Inc, ³Chhattisgarh Swami Vivekanand Technical University

4:25PM
2A.3
Robust Transistor Sizing for Improved Performances in Digital Circuits using Optimization Algorithms
Prateek Gupta¹, Harshini Mandadapu², Shirisha Gourishetty², Zia Abbas^2
1IIIT H, ²International Institute of Information Technology, Hyderabad

4:45PM
2A.4
Resilient Reorder Buffer Design for Network-on-Chip
Zheng Xu¹ and Jacob Abraham^2
1ARM, Inc., ²University of Texas

5:05PM
2A.5
Simulation Based Assessment of SRAM Data Retention Voltage
Zhipeng Dong, Xi Cao, Vivek Joshi, Muhammed Ahosan Ul Karim, Torsten Klick, Joerg Schmid
GLOBALFOUNDRIES

Chair: Dr. Brajesh Kumar Kaushik, Indian Institute of Technology-Roorkee
Co-Chair: Swaroop Ghosh, Pennsylvania State University

3:45PM
2B.1
Evaluating Design Space Subsetting for Multi-Objective Optimization in Configurable Systems
Mohamad Hammam Alsafrjalani¹, Tosiron Adegbija², Lokesh Ramamoorthi^1
1University of Miami, ²University of Arizona

4:05PM
2B.2
A Scalable Image/Video Processing Platform with Open Source Design and Verification Environment
Xiaokun Yang¹, Yunxiang Zhang¹, Lei Wu^2
1University of Houston Clear Lake, ²Auburn University at Montgomery

4:25PM
2B.3
Power-aware IoT based Smart Health Monitoring using Wireless Body Area Network
Jitumani Sarma¹, Akash Katiyar², Rakesh Biswas², Hemanta Kumar Mondal^2
1Indian Institute of Information Technology, Guwahati, ²Indian Institute of Information Technology Guwahati, India

4:45PM
2B.4
A Comprehensive Evaluation of Power Delivery Schemes for Modern Microprocessors
Jawad Haj-Yahya¹, Efraim Rotem², Avi Mendelson³, Anupam Chattopadhyay^4
1School of Computer Science and Engineering, Nanyang Technological University, ²CPU Architect, Intel, Israel, ³EE and CS Technion, Israel, ⁴Nanyang Technological University

5:05PM
2B.5
State Preserving Dynamic DRAM Bank Re-Configurations for Enhanced Power Efficiency
Kaustav Goswami¹, Hemanta Kumar Mondal¹, Shirshendu Das², Dip Sankar Banerjee^2
1Indian Institute of Information Technology Guwahati India, ²Indian Institute of Information Technology Guwahati

Chair: Shomit Das, AMD Research
Co-Chair: Aswin Mehta, Texas Instruments

3:45PM
2C.1
Deterministic Stochastic Computation Using Parallel Datapaths
Alexander Groszewski and Travis Lenz
University of Texas at Austin

4:05PM
2C.2
MAPIM: Mat Parallelism for High Performance Processing in Non-volatile Memory Architecture
Joonseop Sim¹, Minsu Kim², Yeseong Kim³, Saransh Gupta⁴, Behnam Khaleghi⁴, Tajana Rosing^5
1University of California, Sandiego, ²University of Minnesota, ³University of California San Diego, ⁴University of California, San Diego, ⁵UCSD

4:25PM
2C.3
Amoeba-Inspired Stochastic Hardware SAT Solver
Kazuaki Hara¹, Naoki Takeuchi², Masashi Aono³, Yuko Hara-Azumi^1
1Tokyo Institute of Technology, ²Yokohama National University, ³Keio University

4:45PM
2C.4
Accelerating Deterministic Bit-Stream Computing with Resolution Splitting
M. Hassan Najafi¹, Sayed Abdolrasoul Faraji², Bingzhe Li², David Lilja², Kia Bazargan^3
1University of Louisiana at Lafayette, ²University of Minnesota, Twin Cities, ³University of Minnesota

5:05PM
2C.5
High-Performance NoCs employing the DSP48E1 blocks of the Xilinx FPGAs
Prabhu Prasad B M¹, Khyamling parane², Basavaraj Talawar^3
1National Institute of Technology Karnataka, Surathkal, ²National Institute of Technology Karnataka, ³CSE, NITK, Surathkal

Chair: Dr. Sicheng Li, HPE
Co-Chair: Pravin Kumar Venkatesan, Velodyne LiDAR

10:00AM
3A.1
MReC: A Multilayer Photonic Reservoir Computing Architecture
Dharanidhar Dhang, Syed Ali Hasnain, Rabi Mahapatra
Texas A&M University

10:20AM
3A.2
Dynamic Reconfiguration of CNNs for Input-Dependent Approximation
Maedeh Hemmat¹ and Azadeh Davoodi^2
1University of Wisconsin-Madison, ²University of Wisconsin, Madison

10:40AM
3A.3
An Application Specific Processor Architecture with 3D Inetegration for Recurrent Neural Networks
Sumon Dey and Paul D. Franzon
North Carolina State University

11:00AM
3A.4
Task-Based Neuromodulation Architecture for Lifelong Learning
Anurag Daram¹, Dhireesha Kudithipudi¹, Angel Yanguas-Gil^2
1Rochester Institute of Technology, ²Argonne National Laboratory,Lemont

Chair: Dr. Lin Yuan, Amazon
Co-Chair: Anupam Chattopadhyay, Nanyang Technological University

10:00AM
3B.1
PUF-PassSE: A PUF based Password Strength Enhancer for IoT Applications
Qian Wang¹, Mingze Gao², Gang Qu^3
1University of Maryland, ²University of Maryland, College Park, ³Univ. of Maryland, College Park

10:20AM
3B.2
On SAT-Based Attacks On Encrypted Sequential Logic Circuits
Yasaswy Kasarabada, Suyuan Chen, Ranga Vemuri
University of Cincinnati

10:40AM
3B.3
A Darwinian Genetic Algorithm for State Encoding Based Finite State Machine Watermarking
Matthew Lewandowski and Srinivas Katkoori
University of South Florida

11:00AM
3B.4
Lightweight Secure-Boot Architecture for RISC-V System-on-Chip
Jawad Haj-Yahya¹, Ming Ming Wong², Vikramkumar Pudi³, Shivam Bhasin⁴, Anupam Chattopadhyay^4
1Agency for Science Technology and Research (ASTAR), ²NanyangTechnologicalUniversity, ³Indian Institute of Technology Tirupati, ⁴Nanyang Technological University

Chair: Prof. Vita Hu, National Central University, Taiwan
Co-Chair: Aswin Mehta, Texas Instruments

10:00AM
3C.1
VeriSFQ: A Semi-formal Verification Framework and Benchmark for Single Flux Quantum Technology
Alvin D. Wong¹, Kevin Su¹, Hang Sun¹, Arash Fayyazi¹, Massoud Pedram², Shahin Nazarian^1
1University of Southern California, ²USC

10:20AM
3C.2
Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications
Ya-Chi Huang, Meng-Hsueh Chiang, Shui-Jinn Wang
National Cheng Kung University

10:40AM
3C.3
Impact of Self-heating on Performance and Reliability in FinFET and GAAFET Designs
Vidya A. Chhabria and Sachin S. Sapatnekar
University of Minnesota

11:00AM
3C.4
Device Designs and Analog Performance Analysis for Negative-Capacitance Vertical-Tunnel FET
Hung-Han Lin and Vita Pi-Ho Hu
National Central University

Chair: Dr. Amey Kulkarni, Velodyne LiDAR
Co-Chair: Dr. Abhilash Goyal, Velodyne LiDAR

11:40AM
4A.1
Behavioral Modeling of Tunable I/O Drivers with Pre-emphasis Using Neural Networks
Huan Yu¹, Jaemin Shin², Tim Michalka², Mourad Larbi¹, Madhavan Swaminathan^1
1Georgia Institute of Technology, ²Qualcomm Technologies, Inc.

12:00PM
4A.2
Small Memory Footprint Neural Network Accelerators
Kenshu Seto¹, Hamid Nejatollahi², Jiyoung An³, Sujin Kang⁴, Nikil Dutt^2
1Tokyo City University, ²University of California, Irvine, ³Kyung Hee University, ⁴Hanyang University

12:20PM
4A.3
Minimizing Classification Energy of Binarized Neural Network Inference for Wearable Devices
Morteza Hosseini¹, Hirenkumar Paneliya¹, Utteja Panchakshara Kallakuri Niyogi², mohit khatwani², Tinoosh Mohsenin^1
1University of Maryland Baltimore County, ²University of Maryland, Baltimore County

12:40PM
4A.4
Exploiting Energy-Accuracy Trade-off through Contextual Awareness in Multi-Stage Convolutional Neural Networks
Katayoun neshatpour, Farnaz Behnia, Houman Homayoun, Avesta Sasan
George Mason University

Chair: Vinod Vishwanath, Real Intent, Inc.
Co-Chair: Sreejit Chakravarty, Intel Corporation

11:40AM
4B.1
Assertion Coverage Aware Trace Signal Selection in Post-Silicon Validation
Xiaobang Liu and Ranga Vemuri
University of Cincinnati

12:00PM
4B.2
A Communication-Centric Observability Selection for Post-Silicon System-on-Chip Integration Debug
Yuting Cao¹, Hao Zheng¹, Sandip Ray^2
1University of South Florida, ²University of Florida

12:20PM
4B.2
Automatic Test Pattern Generation for Double Stuck-at Faults Based on Test Patterns of Single Faults
Peikun Wang¹, Amir Masoud Gharehbaghi², Masahiro Fujita^1
1University of Tokyo, ²The University of Tokyo

12:40PM
4B.2
Deep Learning-Based Wafer-Map Failure Pattern Recognition Framework
Tsutomu Ishida, Izumi Nitta, Daisuke Fukuda, Yuzi Kanazawa
Fujitsu Laboratories Ltd.

Chair: Rung-Bin Lin, Yuan Ze University
Co-Chair: Srinivas Katkoori, University of South Florida

3:40PM
5A.1
Drive-Strength Selection for Synthesis of Leakage-Dominant Circuits
Mahfuzul Islam¹, Shinichi Nishizawa², Yusuke Matsui³, Yoshinobu Ichida^3
1Kyoto University, ²Saitama University, ³ROHM Semiconductor

4:00PM
5A.2
Estimating Pareto Optimum Fronts to Determine Knob Settings in Electronic Design Automation Tools
Billy Huggins, W. Rhett Davis, Paul Franzon
North Carolina State University

4:20PM
5A.3
An Artificial Intelligence Approach to EDA Software Testing: Application to Net Delay Algorithms in FPGAs
Madhu Raman, Nizar Abdallah, Julien Dunoyer
Microsemi

4:40PM
5A.4
Impact of Double-Row Height Standard Cells on Placement and Routing
Rung-Bin Lin and Yu-Xiang Chiang
Yuan Ze University

Chair: Ali A. Shahi, GlobalFoundries
Co-Chair: Vinod Vishwanath, Real Intent, Inc.

3:40PM
5B.1.1
A Non-Slicing 3-D Floorplan Representation for Monolithic 3-D IC Design
Shantonu Das and Dae Hyun Kim
Washington State University

4:00PM
5B.1.2
Routing Complexity Minimization of Monolithic Three-Dimensional Integrated Circuits
Sheng-En(David) Lin and Dae Hyun Kim
Washington State University

Chair: Vinod Vishwanath, Real Intent, Inc.
Co-Chair: Ali A. Shahi, GlobalFoundries

4:20PM
5B.2.1
Towards Energy Efficient non-von Neumann Architectures for Deep Learning
Antara Ganguly¹, Rajeev Muralidhar², Virendra Singh^1
1Indian Institute of Technology, Bombay, ²Telstra Communications

4:40PM
5B.2.2
Closing the Verification Gap with Static Sign-off
Pranav Ashar and Vinod Viswanath
Real Intent, Inc.