Deep Learning-Based Wafer-Map Failure Pattern Recognition Framework

Tsutomu Ishida, Izumi Nitta, Daisuke Fukuda, Yuzi Kanazawa
Fujitsu Laboratories Ltd.


In integrated circuit (IC) manufacturing, wafer-map analysis has been essential for yield improvement. In this study, we focused on wafer-map failure pattern recognition. We proposed a deep learning-based failure pattern recognition framework. The proposed framework needs only wafer-maps with and without target failure patterns to recognize, and ascertains the features of the target failure patterns automatically. Conventional deep learning methods need a large amount of wafer-maps with the target failure patterns as training data for achieving high recognition accuracy. In the proposed framework, a data augmentation technique with noise reduction is proposed, and it is the key to achieve high recognition accuracy if the number of wafer-maps with the target failure patterns is small. Experimental results using a benchmark dataset showed that the proposed framework achieves high recognition accuracy with a failure pattern recognition problem and also multiple failure pattern recognition problem, and we confirmed the effectiveness of the proposed data augmentation technique.