A Non-Slicing 3-D Floorplan Representation for Monolithic 3-D IC Design

Shantonu Das and Dae Hyun Kim
Washington State University


In this paper, we propose a non-slicing 3-D floorplan representation to design low-power block-level monolithic 3-D ICs. The new 3-D floorplan representation applied to the simulated annealing optimization achieves smaller volume, shorter wire length, and lower dynamic power consumption than the Sequence Triple, Sequence Quintuple, and Slicing Tree 3-D floorplanning representations.