Robust Transistor Sizing for Improved Performances in Digital Circuits using Optimization Algorithms

Prateek Gupta1, Harshini Mandadapu2, Shirisha Gourishetty2, Zia Abbas2
1IIIT H, 2International Institute of Information Technology, Hyderabad


In this paper, the optimal transistor sizing of the digital cells has been obtained using Simulated Annealing algorithm and an Artificial Bee Colony algorithm and their results have been compared with nominal results for various nanoscale CMOS digital circuits. The goal is to minimize the leakage power keeping the other performance parameters such as propagation delays and the area in the bound. The simulations are done using HSPICE tool for 45nm and below using Metal gate High k Predictive Technology Model cards. To make sure of the unaffected working of all cells in the automotive applications, the temperature range and supply voltage has been taken between -55degC to 125degC and 0.95V to 70% without any penalty in the critical path delay.