In this paper, we propose a system verification framework for single-flux quantum (SFQ) circuits using the Universal Verification Methodology (UVM) standard. The SFQ technology in consideration is superconducting digital electronic devices that operate at cryogenic temperatures with active circuit elements called the Josephson junction, which operate at high switching speeds and low switching energy – allowing SFQ circuits to operate at frequencies over 300 GHz. Due to key differences between SFQ and CMOS logic, semi-formal verification techniques for the former are not as advanced as the latter. Thus, it is crucial to develop efficient verification techniques as the complexity of SFQ circuits grows. As such, our verification framework focuses on verifying the key circuit and gate-level properties of SFQ logic: fanout, gate-level pipeline, path balancing, and input-to-output latency. The considered combinational circuits in our verification framework are: Kogge-Stone adders (KSA), array multipliers, integer dividers, and select ISCAS‘85 benchmark combinational circuits. Methods of introducing bugs into the SFQ circuit designs for verification detection were experimented with – including stuck-at faults, fanout errors, unbalanced paths, and functional bugs like incorrect combinational gates. In addition, we propose SFQ benchmark circuits that exemplify the properties of SFQ logic and present our verification framework’s performance on these benchmark circuits. The portability and reusability of the UVM standard allows our framework to serve as a foundation for future SFQ semi-formal verification techniques.