Lightweight Secure-Boot Architecture for RISC-V System-on-Chip

Jawad Haj-Yahya1, Ming Ming Wong2, Vikramkumar Pudi3, Shivam Bhasin4, Anupam Chattopadhyay4
1Agency for Science Technology and Research (ASTAR), 2NanyangTechnologicalUniversity, 3Indian Institute of Technology Tirupati, 4Nanyang Technological University


Securing thousands of connected, resource-constrained computing devices is a major challenge nowadays. Adding to the challenge, third party service providers need regular access to the system. To ensure the integrity of the system and authenticity of the software vendor, secure boot is supported by several commercial processors. However, the existing solutions are either complex, or have been compromised by determined attackers. In this scenario, open-source secure computing architectures are poised to play an important role for designers and white hat attackers.

In this manuscript, we propose a lightweight hardware-based secure boot architecture. The architecture uses efficient implementation of Elliptic Curve Digital Signature Algorithm (ECDSA), Secure Hash Algorithm 3 (SHA3) hashing algorithm and Direct Memory Access (DMA). In addition, the architecture includes Key Management Unit, which incorporates an optimized Physically Unclonable Function (PUF) for providing keys to the security blocks of the SoC, among which, secure boot and remote attestation. We demonstrated the framework on RISC-V based System on Chip (SoC). Detailed analysis of performance and security for the platform is presented.