Approximate Logic Synthesis (ALS) is the process of synthesizing and mapping a given Boolean network with accepting occurrence of errors with bounded magnitude and/or rate at the primary outputs. In this paper, we present Q-ALS, an approach for ALS with focus on the technology mapping phase. Q-ALS incorporates reinforcement learning to find the maximum error rate that each node of the given network can tolerate such that a maximum saving in delay and area is achieved. More precisely, the Maximum Hamming Distance (MHD) between exact and approximate truth tables of cuts of each node is determined using the Q-learning algorithm. A Q-Learning agent is trained with a sufficient number of iterations aiming to select the fittest values of MHD for each node. Finally, in a cut-based technology mapping approach, the best supergates (in terms of delay and area bounded further by the fittest MHD) are selected towards implementing each node. Experimental results show that having set the required accuracy of 95% at the primary outputs, Q-ALS reduces the total cost in terms of area and delay by up to 70% and 36%, respectively, and also reduces the run-time by 2.21 times on average, when compared to a state-of-the-art academic ALS tool.