In this paper we demonstrate how artificial intelligence approaches such as machine learning present an efficient technique for testing key aspects of an EDA software and for validating its quality of results, especially in the context of FPGA architectures. We explain how we apply this approach to the case of testing and quality verification of AWE-based delay estimation algorithm of routing nets in an FPGA fabric. The proposed testing application uses a machine learning model to identify suspicious net delay calculation errors, which then are flagged for an in-depth targeted verification. The ML model is trained using Spice, a golden delay calculation reference. The ML features are derived from the regularity and repeatability found in FPGAs. Results obtained on a 28nm FPGA benchmark are very promising and show higher than 97% detection rate of randomly injected errors.