Fast Mapping-Based High-Level Synthesis of Pipelined Circuits

Chaofan Li1, Sachin S. Sapatnekar2, Jiang Hu3
1Synopsys Inc., 2University of Minnesota, 3Texas A&M University


High level synthesis (HLS) is often employed as a frequently called kernel in design space exploration (DSE). Therefore, its nontrivial runtime becomes a bottleneck that prevents extensive solution search in DSE. In this work, we develop a mapping-based HLS technique that is fast and friendly to local incremental changes. It exploits the static-single assignment (SSA)-form intermediate representation (IR), starts with direct mapping from the IR to a fully pipelined circuit and performs incremental resource sharing in an iterative manner, which then alters the fully pipelined circuit to a partially pipelined or nonpipelined circuit. An algorithm is also proposed for automatic synthesis of pipeline interlocks to avoid structural hazards incurred by resource conflicts. Experimental results show that the proposed method is 74× faster than a state-of-the-art commercial HLS tool. At the same time, it can achieve the same or better circuit performance in terms of throughput.