Resilient Reorder Buffer Design for Network-on-Chip

Zheng Xu1 and Jacob Abraham2
1ARM, Inc., 2University of Texas


Functionally safe control logic design without full duplication is difficult due to the complexity of random control logic design. Reorder buffer (ROB) is a control logic function commonly used in high performance computing system design. In this study, we focused on safe ROB design used in an industry quality Network-on-Chip (NOC) AXI4 Network Interface (NI) block. We developed and applied several area efficient safe design techniques with both theoretical analysis and formal proof and showed that we can achieve functionally safe diagnostic error coverage over 99\% with 20\% of extra area and power overhead and no performance degradation.