Closing the Verification Gap with Static Sign-off

Pranav Ashar and Vinod Viswanath
Real Intent, Inc.


It is commonly held that because SOCs are extremely complex, the gap between the ability to design and to verify is beyond manageable proportions. Recent reality, though, has been more positive. The recent increase in SOC scale has been enabled by design-style advances, and the increase in SOC scale has been much more rapid than that of constituent IP. Consequently, verification complexity and SOC failure is now more correlated to SOC implementation schemes than IP functionality. In this milieu, SOC sign-off appears more manageable when broken into verification problems posed by the individual SOC implementation schemes, each scheme characterized by a narrow range of failure risks that can be modeled precisely. This tends to be a sweet spot for “static analysis”, which is a general term for methods that are based on algorithmically analyzing design attributes rather than testing a design by evaluating input stimuli through them. In fact, the dissection of SOC verification into the individual verification problems and the development of failure-specific static analysis methods for them has been the verification revolution of the past decade, without which the SOC revolution would have stalled.