For a highly duty-cycled IoT device, where the circuit spends most of the time in sleep mode, leakage-energy becomes the dominant energy consumption source. Therefore, circuit design to reduce the leakage-power has become a critical issue. The state-of-the-art standard-cell library is optimized for high-performance designs. In this paper, we show that choosing a suitable set of drive-strengths can reduce the leakage-energy by multiple times. To realize the suitable set, cells with larger gate-lengths or stacked devices are essential although they increase cell area and gate capacitance. The holistic property of a standard-cell library ensures that a better circuit can be synthesized with the slow cells in the library. Experimental results using ISCAS’85 circuits show a maximum of 50 % reduction of leakage power at 0.1 MHz operation.