Automatic Test Pattern Generation for Double Stuck-at Faults Based on Test Patterns of Single Faults

Peikun Wang1, Amir Masoud Gharehbaghi2, Masahiro Fujita1
1University of Tokyo, 2The University of Tokyo


Multiple faults are more likely to occur in the fabricated circuits since they have been becoming larger and denser in the past decades. There have been researches that propose the ATPG method to deal with double faults by quickly selecting all the undetected faults by the test patterns for the single fault, and then generating the additional test patterns for those undetected faults. However, the generated test patterns may not be complete to cover all the double faults, and the test generation process cannot be completed in an acceptable runtime. In order to solve those problems, we propose an improved ATPG method which can detect all the double faults, covering all the missing cases ignored by the previous research. Moreover, the execution time is significantly reduced by adequately integrating all the external tools and programs, as well as employing strategies such as circuit partitioning and bit parallel processing to accelerate the speed of the fault simulation and the SAT process. To fully understand the performance of the proposed method, we comprehensively analyze the experimental results in several different aspects, which demonstrate that our method can quickly generate compact test patterns for double stuck-at faults on the circuits whose single stuck-at faults can be generated. Since the proposed method efficiently generates test patterns for the remaining double faults that cannot be detected given the test patterns for single faults, it can be inductively extended to generate test patterns for triple faults, quadruple faults, ..., to cover all multiple faults.