Chair: Suyash Ranjan, Qualcomm, San Diego

10:20AM
1A.1
HISPE: High-Speed Configurable Floating-Point Multi-Precision Processing Element
Tejas N¹, Rakshit Bhatia¹, Madhav Rao^2
1IIIT-Bangalore, ²International Institute of Information Technology-Bangalore

10:40AM
1A.2
A 0.186 pJ/bit, 6-Gb/s, Energy-Efficient, Half-Rate Hybrid Circuit Topology in 1.2V, 65 nm CMOS.
Prema Kumar Govindaswamy¹, Mursina Khatun², Vijay Shankar Pasupureddi^1
1Indian Institute of Technology Bhubaneswar, ²a23ec09005@iitbbs.ac.in

11:00AM
1A.3
A 1.2 V Double-Tail StrongARM Latch Comparator with 51 fJ/comparison and 380 μV Input Noise in 65 nm CMOS Technology
Srinivasa Rao Maram¹, Boyapati Subrahmanyam², Vijay Shankar Pasupureddi^1
1Indian Institute of Technology Bhubaneswar, ²FH-Kaernten

11:20AM
1A.4
HiCTL: High Fan-in Differential Capacitive-Threshold-Logic Gate Implementation With An Offset-Compensated Comparator
Abdullah Sahruri¹, Martin Margala¹, Ugur Cilingiroglu^2
1University of Louisiana at Lafayette, ²Yeditepe University

Chair: Chidhambaranathan R, Synopsys Inc.

10:20AM
1B.1
Quantum Circuit Simulation with Fast Tensor Decision Diagram
Qirui Zhang, Mehdi Saligane, Hun Seok Kim, David Blaauw, Georgios Tzimpragos, Dennis Sylvester
University of Michigan

10:40AM
1B.2
Dual Use Circuitry for Early Failure Warning and Test
Alexander Coyle¹, Hui Jiang¹, Jennifer Dworak¹, Theodore Manikas¹, Kundan Nepal^2
1Southern Methodist University, ²University of St Thomas

11:00AM
1B.3
RTL Simulation Acceleration with Machine Learning Models
Chandan Karfa¹, Surajit Das², Hetang Patel³, Disha Puri⁴, Anshul Jain⁴, Kartheek Bellamkonda³, Rahul Reddy³, Arijit Sur³, Pradip Prajapati^5
1Indian Institute of Technology Guwahati, ²Postdoctoral Research Associate, ³IIT Guwahati, ⁴Intel, ⁵Inrtel

11:20AM
1B.4
Automated Assertion Checker Generator and Information Flow Tracking for Security Verification
Miguel Alfaro Zapata, Amirhossein Shahshahani, Zeljko Zilic
McGill University

Chair: Hossein Sayadi, California State University, Long Beach

10:20AM
1C.1
DECOR: Enhancing Logic Locking Against Machine Learning-Based Attacks
Yinghua Hu¹, Kaixin Yang², Subhajit Dutta Chowdhury², Pierluigi Nuzzo^2
1Synopsys, ²University of Southern California

10:40AM
1C.2
TEE-Time: A Dynamic Cache Timing Analysis Tool for Trusted Execution Environments
Quentin Forcioli, Sumanta Chaudhuri, Jean-luc Danger
Telecom Paris

11:00AM
1C.3
Obfuscating Quantum Hybrid-Classical Algorithms for Security and Privacy
Suryansh Upadhyay¹ and Swaroop Ghosh^2
1Penn State University, ²Pennsylvania State University

11:20AM
1C.4
A 5T Half-SRAM Design for Cold CMOS Physical Unclonable Function Applications and Beyond
Rouwaida Kanj¹ and Jamil Kawa^2
1Synopsys (American University of Beirut, on leave), ²Synopsys

11:40AM
1C.5
Model Extraction Attack against On-device Deep Learning with Power Side Channel
Jialin Liu and han wang
Temple University

Chair: Murthy Palla, Synopsys
Co-Chair: Huan Yu, Apple

1:30PM
2A.1
Fake Timer: An Engine for Accurate Timing Estimation in Register Transfer Level Designs
Daniela Sanchez Lopera¹, Robert Kunzelmann¹, Endri Kaja², Wolfgang Ecker^1
1Technical University of Munich & Infineon Technologies AG, ²Technische Universität Kaiserslautern & Infineon Technologies AG

1:50PM
2A.2
High-Level Synthesis for Microfluidic Biochips Considering Actual Volume Management and Channel Storage
Zhengyang Chen¹, Yuhan Zhu¹, Zhen Chen¹, Zhisheng Chen², Genggeng Liu^1
1College of Computer and Data Science, Fuzhou University, ²School of Informatics, Xiamen University

2:10PM
2A.3
Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators
Mahdi Taheri¹, Natalia cherezova², Mohammad Saeed Ansari³, Maksim Jenihhin², ALI Mahani⁴, Masoud Daneshtalab⁵, Jaan Raik^2
1PhD researcher at Tallinn university of Technology, ²Tallinn University of Technology, ³University of Alberta, ⁴Shahid Bahonar University of Kerman, ⁵KTH Royal Institute of Technology

2:30PM
2A.4
Comparative Analysis of Graph Isomorphism and Graph Neural Networks for Analog Hierarchy Labeling
Zhengfeng Wu and Ioannis Savidis
Drexel University

2:50PM
2A.5
SRAM-PG: Power Delivery Network Benchmarks from SRAM Circuits
Shan Shen, Zhiqiang Liu, Wenjian Yu
Tsinghua University

Chair: Mohammad Ashiqur Rahman, Florida International University

1:30PM
2B.1
A Needle in the Haystack: Inspecting Circuit Layout to Identify Hardware Trojans
Xingyu Meng¹, Abhrajit Sengupta², Kanad Basu^1
1University of Texas at Dallas, ²New York University

1:50PM
2B.2
Trojan Assets and Attack Vectors in Processors
Czea Sie Chuah¹, Alexander Hepp², Christian Appold¹, Tim Leinmüller^1
1DENSO Automotive Deutschland GmbH, ²Technical University of Munich, TUM School of Computation, Information and Technology

2:10PM
2B.3
Trojan Attacks on Variational Quantum Circuits and Countermeasures
Subrata Das and Swaroop Ghosh
The Pennsylvania State University

2:30PM
2B.4
FAST-GO: Fast, Accurate, and Scalable Hardware Trojan Detection using Graph Convolutional Networks
Ali Imangholi¹, Mona Hashemi², Amirabbas Momeni¹, Siamak Mohammadi³, Trevor E. Carlson^4
1School of ECE, College of Eng., University of Tehran, ²School of ECE, College of Eng., University of Tehran, and School of Computing, National University of Singapore, ³School of ECE, College of Eng., University of Tehran, and School of Computing Science, IPM, ⁴National University of Singapore

Chair: Cheng Tan, Google

1:30PM
2C.1
Optimizing Layer-Fused Scheduling of Transformer Networks on Multi-accelerator Platforms
Steven Colleman¹, Arne Symons¹, Victor Jung², Marian Verhelst^1
1KULeuven, ²ETH Zurich

1:50PM
2C.2
Roofline Performance Analysis of DNN Architectures on CPU and GPU Systems
Prashanth H C¹ and Madhav Rao^2
1IIIT-Bangalore, ²International Institute of Information Technology-Bangalore

2:10PM
2C.3
PSO Optimized Design of Error Balanced Weight Stationary Systolic Array Architecture for CNN
Dantu Nandini Devi¹, Gandi Ajay Kumar², Bindu G Gowda², Madhav Rao^3
1International Institute of Information Technology Bangalore, ²international institute of information technology, bangalore, ³International Institute of Information Technology-Bangalore

2:30PM
2C.4
DNN Memory Footprint Reduction via Post-Training Intra-Layer Multi-Precision Quantization
Behnam Ghavami¹, Amin Kamjoo¹, Lesley Shannon¹, Steve Wilton^2
1Simon Fraser University, ²UBC

Chair: Cindy Yang Yi, Virginia Tech

9:40AM
PW1.1
Error Distribution Estimation for Fixed-point Arithmetic using Program Derivatives
Soramichi Akiyama¹, Ryota Shioya², Yuto Miyatake³, Tongxin Yang^4
1Ritsumeikan University, ²The University of Tokyo, ³Osaka University, ⁴Sony Semiconductor Solutions Corporation

9:45AM
PW1.2
An Automated Exhaustive Fault Analysis Technique guided by Processor Formal Verification Methods
Endri Kaja¹, Nicolas Gerlin¹, Bihan Zhao¹, Daniela Lopera¹, Jad Halabi¹, Azam Khan¹, Sebastian Prebeck¹, Dominik Stoffel², Wolfgang Kunz², Wolfgang Ecker^1
1Infineon Technologies AG, ²Rheinland-Pfalzische Technische Universität Kaiserslautern-Landau

9:50AM
PW1.3
Timing-Driven High-Level Synthesis for Continuous-Flow Microfluidic Biochips
ZhengYang Ye¹, Zhisheng Chen², Youlin Pan³, Genggeng Liu³, Wenzhong Guo³, Tsung-Yi Ho⁴, Xing Huang^5
1Fuzhou University, ²Xiamen University， Xiamen, ³Fuzhou University, Fuzhou, ⁴Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong, ⁵School of Computer Science, Northwestern Polytechnical University, Xi'an

9:55AM
PW1.4
Swarm - A VLSI Timing, Fanout-aware Clustering Algorithm
Christos Sotiriou¹, George Goudroumanis¹, Nikolaos Sketopoulos¹, Christos Georgakidis^2
1Univesity of Thessaly - Department of Electrical and Computer Engineering (EECE), ²University of Thessaly

10:00AM
PW1.5
FastPASE: An AI-Driven Fast PPA Speculation Engine for RTL Design Space Optimization
Akash Levy¹, Joe Walston², Sourav Samanta², Priyanka Raina¹, Stelios Diamantidis^2
1Stanford University, ²Synopsys, Inc.

10:05AM
PW1.6
MORE-Router+: Multilayer Multi-capacity ORdered Escape Routing via Bus-oriented Layer Assignment
Zhenyi Gao, Sheqin Dong, Zifei Cheng, Wenjian Yu
Tsinghua University

10:10AM
PW1.7
EDA-ML: Graph Representation Learning Framework for Digital IC Design Automation
Pratik Shrestha and Ioannis Savidis
Drexel University

10:15AM
PW1.8
Graph Neural Network-Based Detailed Placement Optimization Framework
DhoUI Lim¹ and Heechun Park^2
1Kookmin University, School of Electrical Engineering, ²UNIST

10:20AM
PW1.9
Ultra-Low Voltage Enablement for Standard Cells with Moment based LVF
ROHIT GUPTA, Chiranjeev Grover, Etienne Maurin, Olivier Minez, Jean-arnaud Francois, Sebastien Marchal
STMicroelectronics

10:25AM
PW1.10
Advancing Analog Reservoir Computing through Temporal Attention and MLP Integration
Khalil Sedki and Yang Yi
Virginia Tech

Chair: Hossein Sayadi, California State University, Long Beach

9:40AM
PW2.1
Unleashing Energy-Efficiency: Neural Architecture Search without Training for Spiking Neural Networks on Loihi Chip
Shiya Liu and Yang Yi
Virginia Tech

9:45AM
PW2.2
Composite Sub-surface Model for RF GaN-HEMTs
Xing Zhou¹, Wanlan Yang¹, Siau Ben Chiah^2
1Nanyang Technological University, ²New Silicon Corporation Pte Ltd

9:50AM
PW2.3
RASH: Reliable Deep Learning Acceleration using Sparsity-based Hardware
Shamik Kundu¹, ARNAB RAHA², Deepak Mathaikutty², Kanad Basu^1
1University of Texas at Dallas, ²Intel Corporation

9:55AM
PW2.4
Exploring Model Poisoning Attack to Convolutional Neural Network Based Brain Tumor Detection Systems
Kusum Lata¹, Prashant Singh², Sandeep Saini^2
1LNMIIT Jaipur, ²The LNM Institute of Information Technology, Jaipur

10:00AM
PW2.5
Sensitivity Analysis of SOT-MTJs to Manufacturing Process Variation: A Hardware Security Perspective
Mousam Hossain¹, Muhtasim Alam Chowdhury², Ronald DeMara¹, Soheil Salehi^3
1University of Central Florida, ²University of Arizona, ³Department of Electrical and Computer Engineering, University of Arizona

10:05AM
PW2.6
Lightweight Multicast Authentication in NoC-based SoCs
Hansika Weersena and Prabhat Mishra
University of Florida

10:15AM
PW2.7
Trimming The Fat: A Minimum-Security Architecture for Protecting SoC Designs Against Supply Chain Threats
Kshitij Raj¹, Aritra Bhattacharyay², Swarup Bhunia³, Sandip Ray^4
1University of Florida, ²Department of Electrical and Computer Engineering, University of Florida, ³Department of Electrical and Computer Engineering, University of Florida, ⁴Department of Electrical and Computer Engineering, University of Florida, Gainesville

10:20AM
PW2.8
Blending Scheduling Barriers: A Hybrid Approach for FPGA-based Post-Quantum Cryptography
Capucine Berger-Sigrist¹ and Andrea Guerrieri^2
1EPFL, ²EPFL and HES-SO

10:25AM
PW2.9
A Low-cost keyword spotting architecture based on wavelet packets feature extraction for edge devices
Sayed Salehi and Prakash Dhungana
University of Kentucky

Chair: Deliang Fan, Johns Hopkins University

9:40AM
PW3.1
SCORCH: Neural Architecture Search and Hardware Accelerator Co-design with Reinforcement Learning
Siqin Liu and Avinash Karanth
Ohio University

9:45AM
PW3.2
SpotLight: A Hotspot-Greedy, Light-Weighted, and Automated Thermal Modeling Framework for Early Smartphone Design
Chin-Wei Wu¹, Yu-Min Lee², Pei-Yu Huang², Bo-Jiun Yang¹, Tai-Yu Chen¹, Ting-Chang Huang¹, Yen-Lin Lee^1
1MediaTek Inc., ²National Yang Ming Chiao Tung University

9:50AM
PW3.3
Performance-Aware Design of Approximate Integrated MAC Factored Systolic Array Accelerators
Dantu Nandini Devi¹, Gandi Ajay Kumar², Bindu G Gowda², Madhav Rao^3
1International Institute of Information Technology Bangalore, ²international institute of information technology, bangalore, ³International Institute of Information Technology-Bangalore

9:55AM
PW3.4
An Energy-Efficient time Domain Based Compute In-Memory Architecture for Binary Neural Network
Subhradip Chakraborty¹, Dinesh Kushwaha², Abhishek Goel³, Anmol Singla⁴, Anand Bulusu³, Sudeb Dasgupta^3
1RGIPT Uttar Pradesh, ²Student, ³IIT Roorkee, ⁴NIT Uttarakhand

10:00AM
PW3.5
A multi band flexible N-path filter suited for non-contiguous channel aggregation
Chadi Jabbour
Telecom Paris

10:05AM
PW3.6
Hardware Trojans in Quantum Circuits, Their Impacts, and Defense
Rupshali Roy¹, Subrata Das², Swaroop Ghosh^1
1Pennsylvania State University, ²The Pennsylvania State University

10:10AM
PW3.7
Thinking Outside the Clock: Physical Design for Field-coupled Nanocomputing with Deep Reinforcement Learning
Simon Hofmann, Marcel Walter, Lorenzo Servadei, Robert Wille
Technical University of Munich

10:15AM
PW3.8
Non-parametric Greedy Optimization of Parametric Quantum Circuits
Koustubh Phalak and Swaroop Ghosh
Pennsylvania State University

10:20AM
PW3.9
Merits of Time-Domain Computing for VMM - A Quantitative Comparison
Florian Freye¹, Jie Lou¹, Christian Lanius¹, Tobias Gemmeke^2
1Chair of Integrated Digital Systems and Circuit Design at RWTH Aachen University, ²RWTH Aachen University

10:25AM
PW3.10
nvXNOR Design with Enhanced Store Capability for BNN Applications
Zeinab Soueidan¹ and Rouwaida Kanj^2
1American University of Beirut, ²Synopsys, American University of Beirut on Leave

Chair: Chidhambaranathan Rajamanikkam, Synopsys
Co-Chair: Zhong Guan, UC Santa Barbara

10:45AM
3A.1
Fast Current Constraints Generation for Chip Safety
Cedric Feghali and Farid Najm
University of Toronto

11:05AM
3A.2
Toward Early Stage Dynamic Power Estimation: Exploring Alternative Machine Learning Methods and Simulation Schemes
Philipp Fengler¹, Sani Nassif², Ulf Schlichtmann^1
1Technical University of Munich, ²Technical University of Munich & Radyalis

11:25AM
3A.3
A novel virtual prototyping methodology for timing-accurate simulation of AMS circuits
Teo Vallone¹, Hayri Hasou², Ernesto Colizzi², Sara Vinco³, Davide Zoni^1
1Politecnico di Milano, ²Infineon Technologies, ³Politecnico di Torino

11:45AM
3A.4
GridVAE: Fast Power Grid EM-Aware IR Drop Prediction and Fixing Accelerated by Variational AutoEncoder
Yibo Liu and Sheldon Tan
University of Califronia, Riverside

12:05PM
3A.5
Full Stage Delay Calculation Using Full Waveform Propagation and Standard Library CCS Model
Stavros Simoglou¹, Iordanis Lilitsis², Nikolaos Blias², Christos Sotiriou^2
1Synopsys, ²Univesity of Thessaly - Department of Electrical and Computer Engineering (EECE)

Chair: Kang Jun Bai, Air Force Research Laboratory

10:45AM
3B.1
An FPGA-based Max-K-Cut Accelerator Exploiting Oscillator Synchronization Model
Mohammad Khairul Bashar¹, Zheyu Li², Vijaykrishnan Narayanan², Nikhil Shukla^1
1University of Virginia, ²Pennsylvania State University

11:05AM
3B.2
A Comparative Analysis of Microrings Based Incoherent Photonic GEMM Accelerators
Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Oluwaseun Alo, Ishan Thakkar
University of Kentucky

11:25AM
3B.3
A SIMD Dynamic Fixed Point Processing Engine for DNN Accelerators
Gopal Raut¹, PRANOSE EDAVOOR², DAVID SELVAKUMAR³, ritambhara thakur^1
1CDAC Bangalore, ²CENTRE FOR DEVELOPMENT OF ADVANCED COMPUTING, ³C-DAC, BANGALORE

11:45AM
3B.4
Exploring Hardware Activation Function Design: CORDIC Architecture in Diverse Floating Formats
Mahati Basavaraju¹, Vinay R¹, Madhav Rao^2
1International Institute of Information Technology, Bangalore, ²International Institute of Information Technology-Bangalore

Chair: Wen Zhang, Wright State University

10:45AM
3C.1
Single-Ferroelectric FET based Associative Memory for Data-Intensive Pattern Matching
Jiayi Wang, Songyu Sun, Xunzhao Yin
Zhejiang University

11:05AM
3C.2
sLLM: Accelerating LLM Inference using Semantic Load Balancing with Shared Memory Data Structures
Jieyu Lin¹, Sai Qian Zhang², Alberto Leon-Garcia^1
1University of Toronto, ²New York University

11:25AM
3C.3
Hyperdimensional Computing vs. Neural Networks: Comparing Architecture and Learning Process
Dongning Ma¹, Cong Hao², Xun Jiao^1
1Villanova University, ²Georgia Institute of Technology

11:45AM
3C.4
Fused Functional Units for Area-Efficient CGRAs
Ron Jokai, Cheng Tan, Jeff Zhang
ASU

12:05PM
3C.5
Hardware Support for Trustworthy Machine Learning: A Survey
Md Shohidul Islam¹, Ihsen Alouani², Khaled N. Khasawneh^1
1George Mason University, ²CSIT, Queen's University Belfast, UK

Chair: Zhong Guan, UC Santa Barbara
Co-Chair: Ioannis Savidis, Drexel University

2:10PM
4A.1
Design-Technology Co-Optimization with Standard Cell Layout Generator for Pin Configurations
Junghyun Yoon¹ and Heechun Park^2
1Kookmin University, School of Electrical Engineering, ²UNIST

2:30PM
4A.2
Routing Intent Aware Pin Access Point Selection for Standard Cell Designs
Po-Chun Wang, Kai-Jie Ton, Rung-Bin Lin
Yuan Ze University

2:50PM
4A.3
SLO-ECO: Single-Line-Open Aware ECO Detailed Placement and Detailed Routing Co-Optimization
Joong-Won Jeon¹, Andrew Kahng², Jae-Hyun Kang¹, Jaehwan Kim¹, Mingyu Woo^2
1Samsung Foundry, ²UCSD

3:10PM
4A.4
Parasitic Capacitance Patterns Grid Density Binarization and Shifted Reflection Step Sequence Encoding for Dimensionality Reduction
Ping Li and Zhong Guan
Sun Yat-sen University

Chair: Ujjwal Guin, Auburn University

2:10PM
4B.1
Side-channel-driven Intrusion Detection System for Mission Critical Unmanned Aerial Vehicles
Alejandro Almeida, Muneeba Asif, Md Tauhidur Rahman, Mohammad Rahman
Florida International University

2:30PM
4B.2
Deep Learning Enhanced Side Chanel Analysis on CRYSTALS-Kyber
Tuan Hoang, Mark Kennaway, Dung Pham, Son Mai, Ayesha Khalid, Ciara Rafferty, Maire O'Neill
Queen's University Belfast

2:50PM
4B.3
Thermo-Attack Resiliency: Addressing a New Vulnerability in Opto-Electrical Network-on-Chips
Mahdi Hasanzadeh¹, Meisam Abdollahi², Amirali Baniasadi², Ahmad Patooghy^3
1North Carolina A & T State University, ²University of Victoria, ³North Carolina A&T State University

3:10PM
4B.4
Enhanced Detection of Thermal Covert Channel Attacks in Multicore Processors
Krithika Dhananjay¹, Vasilis Pavlidis², Ayse Coskun³, Emre Salman^1
1Stony Brook University, ²University of Manchester, ³Boston University

3:30PM
4B.5
RTL Interconnect Obfuscation By Polymorphic Switch Boxes For Secure Hardware Generation
Haimanti Chakraborty and Ranga Vemuri
University of Cincinnati

Chair: Jeff (Jun) Zhang, Arizona State University

2:10PM
4C.1
Enhancing Self-sustaining IoT Systems with Autonomous and Smart UAV Data Ferry
Mason Conkel¹, Wen Zhang², Chen Pan^3
1The University of Texas at San Antonio (UTSA), ²Wright State University, ³The University of Texas at San Antonio

2:30PM
4C.2
Learning Client Selection Strategy for Federated Learning across Heterogeneous Mobile Devices
Sai Qian Zhang¹, Jieyu Lin², Qi Zhang³, Yu-Jia Chen^4
1New York University, ²University of Toronto, ³Microsoft, ⁴National Central University

2:50PM
4C.3
Deep Learning Based IoT System for Real-time Traffic Risk Notification
Sahidul Islam¹, Seth Klupka², Ramin Mohammadi², Yufang Jin³, Mimi Xie^1
1The University of Texas at San Antonio, ²UTSA, ³University of Texas at San Antonio

3:10PM
4C.4
Learning-Based Secure Spectrum Sharing for Intelligent IoT Networks
Amir Alipour-Fanid¹, Monireh Dabaghchian², Long Jiao³, Kai Zeng^4
1University of the District of Columbia, ²Morgan State University, ³University of Massachusetts Dartmouth, ⁴George Mason University

Chair: Ahmedullah Aziz, The University of Tennessee, Knoxville

9:00AM
5A.1
Design and Evaluation of Parametric NTT Hardware Unit using different Multiplier based Modular Reduction Techniques
Lokesh Maji¹, Aman Prajapati¹, Madhav Rao^2
1International Institute of Information Technology Bangalore, ²International Institute of Information Technology-Bangalore

9:20AM
5A.2
Multi-ALM: Run-time Multi-Level Reconfigurable Approximate Logarithmic Multiplier
Maliha Tasnim, Chinmay Raje, Sheldon Tan
University of California Riverside

9:40AM
5A.3
SRAM-Based Analog Compute-In-Memory Architecture Using C-2C Ladder And Signal Margin Assisted Design Methodology
Dinesh Kushwaha¹, Ashish Joshi², Abhishek Goel³, Rajiv Joshi⁴, Sudeb Dasgupta³, Anand Bulusu^3
1Student, ²Intel India, ³IIT Roorkee, ⁴IBM TJ Watson

10:00AM
5A.4
Efficient Radix-4 Approximated Modified Booth Multiplier for Signal Processing and Computer Vision: A Probabilistic Design Approach
Bindu G Gowda¹, Prashanth H C², Muralidhara V N³, Madhav Rao^3
1International Institute of Information Technology, Bangalore, ²IIIT-Bangalore, ³International Institute of Information Technology-Bangalore

10:20AM
5A.5
Reprogrammable Time-Domain RRAM Based Vector Matrix Multiplier for In-Memory Computing
Bipul Boro, Rushik Parmar, Ashvinikumar Dongre, Gaurav Trivedi
Indian Institute of Technology Guwahati

Chair: Jeff (Jun) Zhang, Arizona State University

9:00AM
5B.1
AutoAnnotate: Reinforcement Learning based Code Annotation for High Level Synthesis
Hafsah Shahzad¹, Ahmed Sanaullah², Sanjay Arora², Ulrich Drepper², Martin Herbordt^1
1Boston University, ²RedHat Inc.

9:20AM
5B.2
Write Intensity based Foresightful Page Migration for Hybrid memories
Aswathy NS¹ and Hemangee Kapoor^2
1IIT Guwahati, ²Indian Institute of Technology Guwahati

9:40AM
5B.3
RTKWS: Real-Time Keyword Spotting Based on Integer Arithmetic for Edge Deployment
Prakash Dhungana and Sayed Salehi
University of Kentucky

10:00AM
5B.4
Bring it On: Kinetic Energy Harvesting to Spark Machine Learning Computations in IoTs
sanket shukla and Sai Manoj Pudukotai Dinakarrao
George mason university

10:20AM
5B.5
Code-Based Cryptography for Confidential Inference on FPGAs: An End-to-End Methodology
Rupesh Karn¹, Johann Knechtel², Ozgur Sinanoglu^2
1New York University, ²New York University Abu Dhabi

Chair: Hossein Sayadi, California State University, Long Beach

9:00AM
5C.1
LLM-FIN: Large Language Models Fingerprinting Attack on Edge Devices
Najmeh Nazari¹, Furi Xiang¹, Chongzhou Fang², Hosein Mohammadi Makrani², Aditya Puri¹, Kartik Patwari¹, Hossein Sayadi³, Setareh Rafatirad⁴, Chen-Nee Chuah¹, Houman Homayoun^4
1UC Davis, ²University of California, Davis, ³California State University, Long Beach, ⁴University of California Davis

9:20AM
5C.2
Always be Pre-Training: Representation Learning for Network Intrusion Detection with GNNs
Zhengyao Gu¹, Diego Lopez¹, Lilas Alrahis², Ozgur Sinanoglu^2
1New York University, ²New York University Abu Dhabi

9:40AM
5C.3
NAND Flash-Based Digital Fingerprinting for Robust and Secure Hardware Authentication
Kamrul Hasan¹, Sara Tehranipoor¹, Nima Karimian¹, Surbhi Vasudeva^2
1West Virginia University, ²San Jose State University

10:00AM
5C.4
Intelligent Malware Detection based on Hardware Performance Counters: A Comprehensive Survey
Hossein Sayadi¹, Zhangying He¹, Hosein Mohammadi Makrani², Houman Homayoun^3
1California State University, Long Beach, ²University of California, Davis, ³University of California Davis

Chair: Rasit Topaloglu, topallabs & Marist College

10:45AM
6A.1
Emerging Reconfigurable Logic Device Based FPGA Design and Optimization
Sheng Lu, Liuting Shang, Sungyong Jung, Chenyun Pan
The University of Texas at Arlington

11:05AM
6A.2
A Low-Dissipation and Scalable GEMM Accelerator with Silicon Nitride Photonics
Venkata Sai Praneeth Karempudi¹, Sairam Sri Vatsavai¹, Ishan Thakkar¹, Oluwaseun Alo¹, Todd Hastings¹, Justin Woods^2
1University of Kentucky, ²Argonne National Lab

11:25AM
6A.3
QNSA: Quantum Neural Simulated Annealing for Combinatorial Optimization
Seongbin Kwon, Dohun Kim, Sunghye Park, Seojeong Kim, Seokhyeong Kang
Pohang University of Science and Technology

11:45AM
6A.4
QuEST: Quantum Circuit Output Estimation using Gaussian Distribution Analysis
Shamik Kundu, Navnil Choudhury, Kanad Basu
University of Texas at Dallas

12:05PM
6A.5
BMX-FPCA: 3D Beyond-Moore Flexible Field Programmable Crossbar Array Architecture
Hasita Veluri and Dilip Vasudevan
Lawrence Berkeley National Laboratory

Chair: Zhen Zhou, Intel

10:45AM
6B.1
EASI-CiM: Event-driven asynchronous Stream-based Image Classifier with Compute-in-Memory kernels
Rahul Sreekumar¹, Minseong Park¹, Mohammad Nazmus Sakib¹, Bhupendra Singh Reniwal², Kyusang Lee¹, Mircea Stan^1
1University of Virginia, ²Indian Institute of Technology Jodhpur

11:05AM
6B.2
Temporal-encoded 6T-RRAM with Bidirectional Control for Future Neuromorphic Systems
Kang Jun Bai¹, Hao Jiang², Zhuwei Qin², Clare Thiem^1
1Air Force Research Laboratory, ²San Francisco State University

11:25AM
6B.3
Time-Domain-Based Non-volatile In-Memory Computing Architecture Using FeFETs for Binary Neural Network
Aditya Sharma, Vatsal Dixit, Dinesh Kushwaha, Nitanshu Chauhan, Vishal Saxena, Sudeb Dasgupta, Anand Bulusu
Indian Institute of Technology Roorkee

11:45AM
6B.4
DESPINE: NAS generated Deep Evolutionary Adaptive Spiking Network for Low Power Edge Computing Applications
Ajay BS¹, Phani Pavan Kambhampati², Madhav Rao^3
1IntelTechnologyIndiaPvtLtd., ²International Institute of Information Technology, Bangalore, ³International Institute of Information Technology-Bangalore

Chair: Ahmedullah Aziz, University of Tennessee, Knoxville

10:45AM
6C.1
Peephole Optimization for Quantum Approximate Synthesis
Joseph Clark and Himanshu Thapliyal
University of Tennessee

11:05AM
6C.2
Optimal quantum simulations of Hamiltonians with symmetries
Itay Hen and Amir Kalev
University of Southern California

11:25AM
6C.3
Continuous Variable Quantum Machine Learning
Kubra Yeter Aydeniz
MITRE Corporation

11:45AM
6C.4
A SPICE-based Emulator Framework for Quantum Error Correction Circuits using classical LC Resonators
Md Mazharul Islam¹, Md. Shafayat Hossain², Ahmedullah Aziz^3
1The University of Tennessee, ²Princeton University, ³University of Tennessee, Knoxville