FPGAs are promising platforms for Post-Quantum Cryptography (PQC) hardware through electronic design automation tools such as High-Level Synthesis (HLS). Previous endeavors on HLS have demonstrated that the incorporation of pragmas and making adjustments to the code can enhance the Quality of Results (QoR). However, manually modifying the original code presents two notable drawbacks: (1) the performance cannot be fully exploited, and (2) it is highly prone to interpretation that may potentially compromise functionality. In this work, our objective is to leverage innovative HLS techniques based on dynamic scheduling that typically does not require any code alterations to maximize performance to the greatest extent possible. In particular, we highlight the benefits of combining static and dynamic HLS and how it opens new challenges for further research in this field.