Detailed placement is a pivotal stage in the VLSI physical design flow, which legalizes all standard cell locations while minimizing cell displacements to maintain the quality of the preceding global placement outcome. In this paper, we present a detailed placement framework leveraging a graph neural network (GNN). Particularly, we formulate detailed placement objectives into a machine learning loss function derived from three distinct goals: eliminating cell overlaps (overlap loss); aligning cells into standard cell rows (location loss); and minimizing cell displacement (displacement loss); The global placement result is transformed into a graph representation, and processed through the GNN model to directly minimize the formulated loss function. Our experimental results demonstrate the effectiveness of the proposed GNN-based detailed placement framework in improving the half-perimeter wirelength (HPWL) and minimizing displacements compared to the state-of-the-art detailed placement algorithm, with an average of 9.82%/13.73% reduction in avg./max displacement and a 2.44% decrease in HPWL.