A 5T Half-SRAM Design for Cold CMOS Physical Unclonable Function Applications and Beyond

Rouwaida Kanj1 and Jamil Kawa2
1Synopsys (American University of Beirut, on leave), 2Synopsys


With the MOSFET characteristics improving dramatically at cryogenic temperatures, a plethora of design opportunities arise. In this paper, we propose a novel 5T Half-SRAM design that exploits cold CMOS operation to offer a versatile solution to SRAM type memories with expanded functionality. The cell latch is not inverter-based and comprises two back-toback PMOS and NMOS transistors. In cold temperature and low leakage operating regimes, the Half-SRAM array serves as an area efficient and data remanence-aware Physical Unclonable Function with temporal tuning capability. The design eliminates the need for voltage ramp-up and power-on/off cycles and rather relies on the inherent properties of the Half-SRAM latch. Statistical simulations were performed using TCAD-generated cold CMOS models with varying threshold voltage distributions. The extracted Physical Unclonable Function responses obtained via the experimental simulations were processed using Python. Experiments targeting the cold temperature range [77K-150K] demonstrate 95% reliability for ±5% VDD fluctuations and response uniqueness ∼ N(50.1%, 1.6%^2)