A 1.2 V Double-Tail StrongARM Latch Comparator with 51 fJ/comparison and 380 μV Input Noise in 65 nm CMOS Technology

Srinivasa Rao Maram1, Boyapati Subrahmanyam2, Vijay Shankar Pasupureddi1
1Indian Institute of Technology Bhubaneswar, 2FH-Kaernten


This paper presents an energy-efficient double-tail strongarm latch (DTSAL) comparator for Internet of Things (IoT) applications, particularly operated with inadequate battery power. The low energy efficiency in the conventional DTSAL comparator is due to the discharge of the preamplifier output nodes even after the latch evaluation is completed. However, the existing solutions improved the energy efficiency of the DTSAL comparator with a degraded performance in either clock-tooutput delay or in input-referred noise voltage. The proposed idea is to provide a high energy efficiency with adequate noise reduction by maintaining the same clock-to-output delay. The high energy efficiency is achieved with an incomplete discharge of the preamplifier output nodes by using an additional transistors along with the tail transistor. These additional transistors are driven by the preamplifier output nodes and complemented outputs of the latch stage. The proposed DTSAL comparator is implemented in 65 nm CMOS process with 1.2 V supply voltage. The proposed DTSAL comparator achieves 51 fJ energy per comparison, a clock-to-output delay of 680 ps, and an inputreferred noise voltage of 380 µV. The proposed DTSAL comparator provides an improvement of 42% in energy reduction and 48% improvement in the figure of merit over the conventional DTSAL comparator.