A 0.186 pJ/bit, 6-Gb/s, Energy-Efficient, Half-Rate Hybrid Circuit Topology in 1.2V, 65 nm CMOS.

Prema Kumar Govindaswamy1, Mursina Khatun2, Vijay Shankar Pasupureddi1
1Indian Institute of Technology Bhubaneswar, 2a23ec09005@iitbbs.ac.in


The traditional hybrid circuit topologies in full- duplex(FD) communication suffer from low-eye opening and high static power consumption at high data rates. In addition, they require gain-stages and sense-amplifier circuit topologies in the receiver path to produce the received signal with rail- to-rail voltage signal swing. As a result, the overall power- budget of the FD transceivers increases due to multiple blocks in the receiver signal path. Hence, the energy-efficiency of the transceiver becomes poor at the cost of increased circuit complexity. To address this issue, in this work, the authors propose a half-rate double tail latch comparator based hybrid (HR-DTLCH) circuit topology deployed at the receiver front- end of the FD transceiver to separate received signal from signal on the interconnect. The proposed DTLCH circuit topology provides strong digital equalization to the received signal at the receiver front-end without need for any power-hungry post signal processing circuitry. The proposed hybrid is designed in 1.2 V, 65 nm CMOS at 6-Gb/s FD data rate over 20 cm FR4-PCB chip-to- chip interconnect. The post-layout simulation results show that the proposed DTLCH circuit topology has power consumption of only 0.56 mW with an energy-efficiency of 0.186 pJ/b at 6-Gb/s FD operation. The final received signal has rail-to-rail output voltage swing with timing jitter of 9 ps. The layout of the DTLCH circuit topology occupies an area of 0.0097 mm^2.