SRAM-Based Analog Compute-In-Memory Architecture Using C-2C Ladder And Signal Margin Assisted Design Methodology

Dinesh Kushwaha1, Ashish Joshi2, Abhishek Goel3, Rajiv Joshi4, Sudeb Dasgupta3, Anand Bulusu3
1Student, 2Intel India, 3IIT Roorkee, 4IBM TJ Watson


In this manuscript, a signal margin-assisted design methodology for a current-based analog compute-in-memory (CIM) architecture is presented. Validation of the design methodology is done on the proposed analog compute-in-memory (CIM) architecture using a C-2C ladder. The effectiveness of an analog CIM architecture depends on the signal margin, scalability, throughput, energy efficiency, computation density, accuracy, and robustness. Hence, we proposed a design methodology to evaluate the effectiveness of an analog CIM architecture at the early design stage. The proposed design methodology can consider the device-level variations to estimate system-level performance and computation accuracy. An evaluation model is also developed to explore the proposed design methodology. LeNet-5 CNN is used to validate the proposed evaluation model. The signal margin of the proposed architecture is 35 mV, which is 2.5× higher than the state-of-the-art. The energy efficiency of the proposed architecture is 1666 TOPS/W at 0.9 V supply voltage in 28 nm CMOS technology. The inference accuracy for the MNIST data set is 98.6 %.