Fast Current Constraints Generation for Chip Safety

Cedric Feghali and Farid Najm
University of Toronto


Electromigration is a reliability concern that affects chip power grids carrying high current over the course of several years. In order to guarantee safety of the chip from void nucleations due to electromigration, a set of current constraints can be generated as a guideline for chip design. In this work, we propose a tool to efficiently generate approximate constraints through model order reduction, based on Arnoldi's algorithm. Our method leverages several properties of the matrices at hand to efficiently perform the required computations in the reduced subspace, before projecting the results back to the original space - leading to 6X speedup when compared to the computation of the exact constraints.