Design-Technology Co-Optimization with Standard Cell Layout Generator for Pin Configurations

Junghyun Yoon1 and Heechun Park2
1Kookmin University, School of Electrical Engineering, 2UNIST


As the technology node scales down toward the deep submicron area (e.g. sub-5nm), design-technology co-optimization (DTCO) becomes imperative to assess the impact of various technology-level options on the design-level benefits. The key challenge of DTCO lies in the extensive engineering efforts and numerous design iterations to analyze the effects of each technology-level option on the final design-level quality. This paper focuses on the option of standard cell pin configuration, and introduces a framework for assessing different pin modulations of standard cells. Particularly, we introduce a standard cell layout generator that automatically builds cell libraries with adaptable pin modification options. Then, we present a comprehensive chip-level design quality analysis with diverse pin configurations generated by our standard cell layout generator. This process facilitates the DTCO of simultaneously optimizing pin accessibility and design power-performance-area (PPA). Our experimental results demonstrate that the proposed standard cell layout generator and design evaluation framework allows a faster iteration for measuring the effects of adjusting standard cell pins in VLSI design quality, which is beneficial in identifying optimal design points for violation-free and high-quality chip design.