FastPASE: An AI-Driven Fast PPA Speculation Engine for RTL Design Space Optimization

Akash Levy1, Joe Walston2, Sourav Samanta2, Priyanka Raina1, Stelios Diamantidis2
1Stanford University, 2Synopsys, Inc.


We develop a tool called FastPASE to rapidly predict design metrics such as power, performance, and area from RTL using graph convolutional networks. FastPASE encodes elaborated RTL netlists as dataflow graphs and applies fan-in/fan-out convolutions based on the connectivity of the nodes. We apply FastPASE to three design case studies: (1) a configurable single instruction multiple data (SIMD) IP, (2) SweRV, an open-source RISC-V core, and (3) randomly-generated combinational RTL. We find that depending on design size, FastPASE can produce predictions 16.7x-155x faster than a commercial physical design tool run up to placement, with excellent predictive capability (average normalized mean absolute error (NMAE) of 13% across all metrics tested for SIMD unit and RISC-V core). On SweRV, we demonstrate that using FastPASE as a proxy metric engine during RTL design space optimization produces improved aggregate design scores in ~13x less time than using full physical design runs. In this context, our tool enables RTL designers to quickly explore the RTL design space and determine the right parameter settings for a particular set of silicon design goals.