ISQED 2010 Program
Tuesday March 23, 2010
SRAM Manufacturability
Chair: Saraju Mohanty
Co-Chair: Valeriy Sukharev
10:30AM
1A.1
Limits of Bias Based Assist Methods in Nano-Scale 6T SRAM
Randy Mann, Satya Nalam, Jiajing Wang, Ben Calhoun
University of Virginia
11:00AM
1A.2
Variability resilient low-power 7T-SRAM design for nano-scaled technologies
Touqeer Azam, Binjie Cheng, David R.S. Cumming
University of Glasgow
11:20AM
1A.3
Robust importance sampling for efficient SRAM yield analysis
Takanori Date1, Shiho Hagiwara1, Kazuya Masu1, Takashi Sato2
1Integrated Research Institute, Tokyo Institute of Technology, 2Kyoto University
11:40AM
1A.4
An Accurate Modeling Method Utilizing Application Specific Statistical Information and Its Application to SRAM Yield Estimation
Hidetoshi Matsuoka, Hiroshi Ikeda, Hiroyuki Higuchi, Yoshinori Tomita
Fujitsu Microelectronics LTD
Tuesday March 23, 2010
Mixed Signal and Power Control Circuits
Chair: Syed Alam
Co-Chair: Mark Budnik
10:30AM
1B.1
Adaptive Power Gating for Function Units in a Microprocessor
Kimiyoshi Usami1, Tatsunori Hashida1, Satoshi Koyama1, Tatsuya Yamamoto1, Daisuke Ikebuchi2, Hideharu Amano2, Mitaro Namiki3, Masaaki Kondo4, Hiroshi Nakamura5
1Shibaura Institute of Technology, 2Keio University, 3Tokyo University of Agriculture and Technology, 4The University of Electro-Communications, 5The University of Tokyo
11:00AM
1B.2
A Dual-Level Adaptive Supply Voltage System for Variation Resilience
Kyu-Nam Shim, Jiang Hu, Jose Silva-Martinez
Department of ECE, Texas A&M University, College Station, TX 77843
11:20AM
1B.3
A Low Power Charge-Redistribution ADC With Reduced Capacitor Array
Mallik Kandala, Ram Gopal Sekar, Chenglong Zhang, Haibo Wang
Southern Illinois University Carbondale
11:40AM
1B.4
Leakage Current Analysis for Intra-Chip Wireless Interconnects
Ankit More and Baris Taskin
Drexel University
Tuesday March 23, 2010
Guaranteeing timing performance
Chair: James Lei
Co-Chair: Fujita
10:30AM
1C.1
Toward Effective Utilization of Timing Exceptions in Design Optimization
Kwangok Jeong, Andrew B. Kahng, Seokhyeong Kang
UC. San Diego
11:00AM
1C.2
Useful clock skew optimization under a multi-corner multi-mode design framework
Weixiang Shen1, Yici Cai1, Wei Chen2, Yongqiang Lu1, Qiang Zhou1, Jiang Hu3
1EDA Lab, Dept. of Computer Science and Technology, Tsinghua University, Beijing, 100084, China, 2Magma Design Automation Inc., 1650 Technology Drive, San Jose, CA 95110, USA, 3Dept. of Electrical and Computer Engineering, Texas A&M University, College Station, TX 77843-3228, USA
11:20AM
1C.3
Clock Buffer Polarity Assignment Considering the Effect of Delay Variations
Minseok Kang and Taewhan Kim
Seoul National University
11:40AM
1C.4
Linear Time Calculation of State-Dependent Power Distribution Network Capacitance
Shiho Hagiwara1, Koh Yamanaga1, Ryo Takahashi2, Kazuya Masu1, Takashi Sato3
1Integrated Research Institute, TokyoInstitute of Technology, 2The University of Tokyo, 3Kyoto University
Tuesday March 23, 2010
Analog Design For Reliability
Chair: Srinivas Bodapati
Co-Chair: Payman Zarkesh-Ha
10:30AM
1D.1
Implementing self-testing and self-repairing analog circuits on field programmable analog array
Venkata Naresh Mudhireddy1, Saravanan Ramamoorthy2, Haibo Wang1
1southern illinois university carbondale, 2southern illinois universty carbondale
11:00AM
1D.2
BSIM4-Based Lateral Diode Model for LNA Co-Designed with ESD Protection Circuit
MING-TA YANG, YANG DU, TONY CHANG, EUGENE WORLEY, KEN LIAO, YOU-WEN YAU, GEOFFREY YEAP
QUALCOMM
11:20AM
1D.3
Hot Carrier Effects on CMOS Phase-Locked Loop Frequency Synthesizers
Yang Liu and Ashok Srivastava
Louisiana State University, Baton Rouge
11:40AM
1D.4
A Novel All Digital Fractional-N Frequency Synthesizer Architecture with Fast Acquisition and Low Spur
Jun Zhao and Yong-Bin Kim
Northeastern University
Tuesday March 23, 2010
Lithography & Manufacturing
Chair: Fedor Pikus
Co-Chair: Valeriy Sukharev
1:30PM
2A.1
Photomasks and the Enablement of Circuit Design Complexity
Peter Buck, Franklin Kalk, Craig West
Toppan Photomasks, Inc.
2:00PM
2A.2
High performance source optimization using a gradient based method in optical lithography
Yao Peng, Jinyu Zhang, Yan Wang, Zhiping Yu
Tsinghua National Laboratory for Information Science and Technology, Institute of Microelectronics, Tsinghua University
2:20PM
2A.3
Suppression of Edge Effects based on Analytic Model for Leakage Current Reduction of sub-40nm DRAM device
Soo Han Choi1, Young Hee Park1, Gyu Tae Kim2
1Samsung Electronics, 2Korea University
2:40PM
2A.4
Assessing Chip-Level Impact of Double-Patterning Lithography
Kwangok Jeong1, Andrew Kahng1, Rasit Topaloglu2
1University of California San Diego, 2GlobalFoundries
Tuesday March 23, 2010
Power Aware Memory Design
Chair: Dinesh Somasekhar
Co-Chair: Jeffrey Fan
1:30PM
2B.1
A 2-Port 6T SRAM Bitcell Design with Multi-Port Capabilities at Reduced Area Overhead
Jawar Singh1, D.S. Aswar2, Dhiraj Pradhan1, S.P. Mohanty3
1University of Bristol, UK, 2, 3University of North Texas, USA
2:00PM
2B.2
Asymmetric 6T SRAM with Two-phase Write and Split Bitline Differential Sensing for Low Voltage Operation
Satyanand Nalam1, Vikas Chandra2, Cezary Pietrzyk2, Robert Aitken2, Benton Calhoun1
1University of Virginia, 2ARM
2:20PM
2B.3
A Robust and Low Power Dual Data Rate (DDR) Flip-Flop Using C-Elements
Srikanth Devarapalli1, Payman Zarkesh-Ha1, Steven Suddarth2
1University of New Mexico, 2COSMIAC
2:40PM
2B.4
Optimizing Power and Throughput for M-Out-Of-N Encoded Asynchronous Circuits
Jun Xu1, Ge Zhang2, Weiwu Hu2
1Institute of Computing Technology, Chinese Academy of Sciences; Graduate Univiersity of Chinese Academy of Sciences, 2Institute of Computing Technology, Chinese Academy of Sciences; Loogson Technology Corporation Limited
Tuesday March 23, 2010
Poster Papers
Chair: Kamesh Gadepally
Co-Chair: Lalitha Immaneni
2D.1
Yield-constrained Digital Circuit Sizing via Sequential Geometric Programming
Yu Ben, Laurent El Ghaoui, Kameshwar Poolla, Costas J. Spanos
Department of EECS, University of California, Berkeley
2D.2
Simultaneous Extraction of Effective Gate Length and Low-field Mobility in Non-uniform Devices
Vivek Joshi1, Kanak Agarwal2, Dennis Sylvester1
1University of Michigan, 2IBM Research Austin
2D.3
Statistical Static Timing Analysis Flow for Transistor Level Macros in a Microprocessor
Vivek Nandakumar1, David Newmark2, Yaping Zhan2, Malgorzata Marek-Sadowska3
1University of California, Santa Barbara, CA, 2Advanced Micro Devices Inc, Austin, TX, 3University of California, Santa Barbara, CA, USA
2D.4
A Framework for Logic-Aware Layout Analysis
Patrick Gibson, Ziyang Lu, Fedor Pikus, Sridhar Srinivasan
Mentor Graphics Corp
2D.5
P3 (Power-Performance-Process) Optimization of Nano-CMOS SRAM using Statistical DOE-ILP
Garima Thakral1, Saraju Mohanty1, Dhruva Ghai1, Dhiraj Pradhan2
1University of North Texas, 2University of Bristol
2D.6
A Yield Improvement Methodology Based on Logic Redundant Repair with a Repairable Scan Flip-Flop Designed by Push Rule
Masanori Kurimoto, Jun Matsushima, Shigeki Ohbayashi, Yoshiaki Fukui, Michio Komoda, Nobuhiro Tsuda
Renesas Technology Corp.
2D.7
A Fault-tolerant Structure for Reliable Multi-core Systems Based on Hardware-Software Co-design
Bingbing Xia, Fei Qiao, Huazhong Yang, Hui Wang
Tsinghua University
2D.8
"Condition-based" Dummy Fill Insertion Method Based on ECP and CMP Predictive Models
Izumi Nitta1, Yuji Kanazawa1, Daisuke Fukuda1, Toshiyuki Shibuya2, Naoki Idani3, Masaru Ito3, Osamu Yamasaki3, Norihiro Harada3, Takanori Hiramoto3
1Fujitsu Laboratories Ltd., 2Fujitsu Laboratories of America, Inc., 3Fujitsu Microelectronics Ltd.
2D.9
Analysis and Modeling of a Low Voltage Triggered SCR ESD Protection Clamp with the Very Fast Transmission Line Pulse Measurement
Jae-Young Park, Jong-Kyu Song, Chang-Soo Jang, Young-Sang Son, Dae-Woo Kim
Dongbu Hitek Co., Ltd.
2D.10
On the Design of Different Concurrent EDC Schemes for S-box and GF(P)
Jimson Mathew1, Hafizur Rahaman1, Abusaleh Jabir2, Saraju Mohanty3, Dhiraj Pradhan1
1University of Bristol, 2Oxford Brookes University, 3Univ of North Texas,
2D.11
Dynamic Forward Body Bias Enhanced Tri-Mode MTCMOS
Hailong Jiao and Volkan Kursun
The Hong Kong University of Science and Technology
2D.12
Adaptive HCI-aware Power Gating Structure
Kyung Ki Kim, Haiqing Nan, Ken Choi
Illinois Institute of Technology
2D.13
Soft Error Rate Determination for Nanoscale Sequential Logic
Fan Wang1 and Vishwani Agrawal2
1Juniper Netwrok, Inc., 2Auburn University
2D.14
Ultra Low-voltage, rail-to-rail input/output stage Operational Transconductance Amplifier (OTA) with high linearity and its application in a Gm-C filter
Farzan Rezaei and Seyed Javad Azhari
Department of Electronics/Electronics Research Center, Iran University of Science and Technology (IUST)
2D.15
A 2.4GHz 1.8-V CMOS Sub-Harmonic Mixer
Mitra Gilasgar
Guilan University
2D.16
Formula-Oriented Compositional Minimization in Model Checking
Bowen Chen1, Haihua Shen1, Wenhui Zhang2
1Institute of Computing Technology, Chinese Academy of Sciences, 2Institute of Software, Chinese Academy of Sciences
2D.17
A Novel Two-Dimensional Scan-Control Scheme for Test-Cost Reduction
Chia-Yi Lin and Hung-Ming Chen
National Chiao Tung University
2D.18
Accelerating Trace Computation in Post-Silicon Debug
Johnny Kuan, Steven Wilton, Tor Aamodt
University of British Columbia
2D.19
Structural Fault Collapsing by Superposition of BDDs for Test Generation in Digital Circuits
Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman
Tallinn University of Technology
2D.20
A Novel Probabilistic SET Propagation Method
Sreenivas Gangadhar and Spyros Tragoudas
Southern Illinois University Carbondale
2D.21
Formal Verification of Full-Wave Rectifier using SPICE Circuit Simulation Traces
Kusum Lata and H S Jamadagni
CEDT,Indian Institute of Science,Bangalore, INDIA
2D.22
OBT implementation on an OTA-C band-pass filter
Pablo Petrashin1, Eduardo Romero2, Gabriela Peretti2
1Universidad Católica de Córdoba, 2Universidad Tecnologica Nacional
2D.23
Fast Block-iterative Domain Decomposition Algorithm for IR Drop Analysis in Large Power Grid
Yu Zhong and Martin D. F. Wong
University of Illinois at Urbana Champaign
2D.24
A Non-Parametric Approach to Behavioral Device Modeling
Dragoljub (Gagi) Drmanac, Brendon Bolin, Li-C. Wang
UCSB
Tuesday March 23, 2010
Variability: Design, Test, and Characterization
Chair: Peter O'Shea
Co-Chair: Narendra Devta-Prasanna
3:30PM
3A.1
Robust Gate Sizing by Uncertainty Second Order Cone
Jin Sun and Janet Wang
The University of Arizona
4:00PM
3A.2
Is Built-In Logic Redundancy Ready for Prime Time?
Chris Allsup
Synopsys, Inc.
4:30PM
3A.3
Variation-Aware Speed Binning of Multi-core Processors
John Sartori1, Ashish Pant2, Rakesh Kumar1, Puneet Gupta2
1Illinois, 2UCLA
4:50PM
3A.4
Use of Scalable Parametric Measurement Macro to Improve Semiconductor Technology Characterization and Product Test
Jeanne Bickford, Nazmul Habib, John Goss, Robert McMahon, Rajiv Joshi, Rouwaida Kanj
IBM
5:10PM
3A.5
Accurate Multi-Specification DPPM Estimation Using Layered Sampling Based Simulation
Ender Yilmaz
Arizona State University
Tuesday March 23, 2010
Emerging Device and Design Techniques
Chair: Paul Tong
Co-Chair: Bao Liu
3:30PM
3B.1
Scalability of PCMO-based Resistive Switch Device in DSM Technologies
Yiran Chen1, Wei Tian1, Hai Li2, Xiaobin Wang1, Wenzhong Zhu1
1Seagate Technnology LLC, 2Polytechnic Institute of NYU
4:00PM
3B.2
A Low Power System with Adaptive Data Compression for Wireless Monitoring of Physiological Signals and its Application to Wireless Electroencephalography
Jeremy Tolbert, Pratik Kabali, Simeranjit Brar, Saibal Mukhopadhyay
Georgia Institute of Technology
4:30PM
3B.3
Modeling and Analysis of III-V Logic FETs for Devices and Circuits: Sub-22nm Technology III-V SRAM Cell Design
Saeroonter Oh, Jeongha Park, S. Simon Wong, H.-S. Philip Wong
Stanford University
4:50PM
3B.4
Die-level Leakage Power Analysis of FinFET Circuits Considering Process Variations
Prateek Mishra, Ajay Bhoj, Niraj Jha
Princeton University
5:10PM
3B.5
Using Time-Aware Memory Sensing to Address Resistance Drift Issue in Multi-Level Phase Change Memory
Wei Xu and Tong Zhang
ECSE Department, Rensselaer Polytechnic Institute
Tuesday March 23, 2010
Power and performance issues in system-level design
Chair: Lech Jóźwiak
Co-Chair: Rajesh Berigei
3:30PM
3C.1
Minimizing the Power Consumption of a Chip Multiprocessor System under an Average Throughput Constraint
Mohammad Ghasemazar, Ehsan Pakbaznia, Massoud Pedram
University of Southern California
4:00PM
3C.2
Design of Low-Power Variation Tolerant Signal Processing Systems with Adaptive Finite Word-length Configuration
Yang Liu1, Jibang Liu2, Tong Zhang2
1Juniper Networks, 2Rensselaer Polytechnic Institute
4:30PM
3C.3
Quality-driven Methodology for Demanding Accelerator Design
Lech Jóźwiak and Yahya Jan
Eindhoven University of Technology
4:50PM
3C.4
Thermal-Aware Job Allocation and Scheduling for Three Dimensional Chip Multiprocessor
Shaobo Liu, Jingyi Zhang, Qing Wu, Qinru Qiu
State University of New York at Binghamton
5:10PM
3C.5
Thermal-Aware Lifetime Reliability in Multicore Systems
Shengquan Wang1 and Jian-Jia Chen2
1University of Michigan-Dearborn, 2ETH Zurich
Tuesday March 23, 2010
Poster Papers
Chair: Kamesh Gadepally
Co-Chair: Lalitha Immaneni
3D.1
A Comprehensive Model for Gate Delay under Process Variation and Different Driving and Loading Conditions
Mingzhi Gao, Zuocang Ye, Yan Wang, Zhiping Yu
Tsinghua National Laboratory for Information Science and Technology, Institute of Microelectronics, Tsinghua Univ., Beijing
3D.2
Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology
Vinayak Honkote and Baris Taskin
Drexel University
3D.3
A MATLAB®-Based Technique for Defect Level Estimation Using Data Mining of Test Fallout Data versus Fault Coverage
Kanad Chakraborty
Cypress Semiconductor
3D.4
Multi-programming environment for Structure Under Pads ( SUP) and Via Arrays Pattern Recognition Automated Classification System
Suraya Mohd Yusof1 and Lau Meng Tee2
1EM_CAD, 2EM-CAD
3D.5
Constraint Analysis and Debugging for Multi-Million Instance SoC Designs
Long Fei, Loa Mize, Cho Moon, Bill Mullen, Sonia Singhal
Synopsys Inc
3D.6
VARIATION AWARE GUARD-BANDING FOR SOC STATIC TIMING ANALYSIS
Vee Kin Wong and Siong Kiong Teng
Intel Microelectronics (M) Sdn. Bhd.
3D.7
Asymmetric Issues of FinFET Device after Hot Carrier Injection and Impact on Digital and Analog Circuits
Chenyue Ma, Hao Wang, Xiufang Zhang, Frank He, Yadong He, Xing Zhang, Xinnan Lin
The Key Laboratory of Integrated Microsystems, School of Computer & Information Engineering, Peking University Shenzhen Graduate School, Shenzhen 518055, P. R. China
3D.8
A novel low voltage current compensated high performance current mirror/NIC
Khalil Monfaredi, Hassan Faraji Baghtash, Seyed Javad Azhari
Iran university of science and technology (IUST)
3D.9
Domino Gate with Modified Voltage Keeper
Jinhui Wang1, Wuchen Wu2, Na Gong2, Ligang Hou2
1Beijing University of Technology, 2
3D.10
Leakage Temperature Dependency Modeling in System Level Analysis
Huang Huang, Gang Quan, Jeffrey Fan
Florida International University
3D.11
Process Variation Tolerant On-Chip Communication Using Receiver and Driver Reconfiguration
Ethiopia Nigussie, Juha Plosila, Jouni Isoaho
University of Turku
3D.12
Calibration of On-Chip Thermal Sensors using Process Monitoring Circuits
Basab Datta and Wayne Burleson
University of Massachusetts-Amherst
3D.13
New SRAM Design Using Body Bias Technique for Ultra Low Power Applications
Fasrhad Moradi1, Dag Wisland2, Hamid Mahmoodi3, Yngvar Berg2, Cao Tuan Vu2
1Purdue University ( University of Oslo), 2University of Oslo, 3SanFrancisco State University
3D.14
Body Bias Driven Design Synthesis for Optimum Performance per Area
Maurice Meijer and Jose Pineda de Gyvez
NXP Semiconductors
3D.15
Methodology to ensure circuit robustness and exceptional silicon quality while proliferating designs across process revisions with high productivity
Nitin Srimal
intsys
3D.16
A Multilevel Multilayer Partitioning Algorithm For Three Dimensional Integrated Circuits
Yu Cheng Hu, Yin Lin Chung, Mely Chen Chi
Chung Yuan Christian University
3D.17
Low Power Clock Gates Optimization For Clock Tree Distribution
Siong Kiong Teng1 and Dr Norhayati Soin2
1Penang Design Center, Intel Microelectronics, Penang, Malaysia, 2Dept. of Electrical Engineering, University of Malaya, Kuala Lumpur, Malaysia
3D.18
An Innovative Method to Automate the Waiver of IP-Level DRC Violations
John Ferguson, Sandeep Koranne, David Abercrombie
Mentor Graphics
3D.19
Post-Synthesis Sleep Transistor Insertion for Leakage Power Optimization in Clock Tree Networks
Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, Alex Veidenbaum, Fadi Kurdahi
UCI
3D.20
Discharge-Path-Based Jumper Insertion and Layer Assignment Techniques for Fixing Antenna Violations in X-Architecture Clock Tree
Chia-Chun Tsai1, Chung-Chieh Kuo2, Lin-Jeng Gu2, Trong-Yen Lee2
1Dept. of Computer Science and Information Engineering, Nanhua University, Taiwan, 2Graduate Institute of Computer and Communication Engineering, National Taipei University of Technology, Taiwan
3D.21
Synthesis and Formal Verification of On-Chip Protocol Transducers through Decomposed Specification
Masahiro Fujita, Hideo Tanida, Fei Gao, Tasuku Nishihara, Takeshi Matsumoto
University of Tokyo
3D.22
Level Matrix Propagation for Reliability Analysis of Nano-scale Circuits based on Probabilistic Transfer Matrix
Hicham Ezzat1 and Lirida Naviner2
1UFE (Universite Francaise d'Egypte), 2Telecom ParisTech
3D.23
Low Power Low Phase Noise CMOS PLL
Abishek Mann, Amit Karalkar, Lili He, Morris Jones
san jose state university
3D.24
Novel Low-Power 12-bit SAR ADC Architecture for RFID Tags
Daniela De Venuto1, Eduard Stikvoort2, Youri Ponomarev3, David Castro3
1Politecnico di Bari - Italy, 2Eindhoven, Netherland, 3NXP Leuven, Belgium
3D.25
Adaptive Task Allocation for Multiprocessor SoCs in Real-Time Energy Harvesting Systems
Tongquan Wei1, Yonghe Guo2, Xiaodao Chen2, Shiyan Hu2
1Computer Science and Technology department, East China Normal University, 2Electrical and Computer Engineering department, Michigan Technological University
Wednesday March 24, 2010
Parametric and delay test
Chair: Srivatsa Vasudevan
Co-Chair: Ramyanshu Datta
10:30AM
4A.1
Real-Time Adaptive Hybrid BiST Solution for Very-Low-Cost ATE Production Testing of Analog to Digital Converters with Optimal DPPM
Sachin D. Dasnurkar and Jacob A. Abraham
Computer Engineering Research Center, The University of Texas at Austin
11:00AM
4A.2
On Evaluating Speed Path Detection of Structural Tests
Jing Zeng1, Jing Wang1, Chia-Ying Chen1, Michael Mateja1, Li-C Wang2
1AMD, 2UCSB
11:20AM
4A.3
Slack Based Approach for Peak Power Reduction during Transition Fault Testing
Manu Baby and Vijay Sarathi
Dubai Circuit Design, DSO
11:40AM
4A.4
Case Studies of Mixed-Signal DFT
Ramyanshu Datta, Mahit Warhadpande, Dale Heaton, S Aarthi, Ram Jonnavithula
Texas Instruments Incorporated
Wednesday March 24, 2010
Package-Chip Co-Design
Chair: Lalitha Immaneni
Co-Chair: Kamesh Gadepally
10:30AM
4B.1
Chip-Package Co-Design in the Analog World for Fast Time To Revenue
Anindya Poddar and Luu Nguyen
Package Technology Group, National Semiconductor Corporation,
Santa Clara, CA
11:00AM
4B.2
Design of Impedance Matching Network in Organic Substrate with Embedded Capacitor Material for SIP Application
Yunfeng Wang
Shenzhen Institute of Advanced Integration Technology, Chinese Academy of Sciences / The Chinese University of Hong Kong
11:20AM
4B.3
Efficient Hierarchical Discretization of Off-chip Power Delivery Network Geometries for 2.5D Electrical Analysis
Mosin Mondal, James Pingenot, Vikram Jandhyala
Dept. of EE, University of Washington
11:40AM
4B.4
Yield Improvement of 3D ICs in the Presence of Defects in Through Signal Vias
Rajeev Nain, Shantesh Pinge, Malgorzata Chrzanowska-Jeske
Portland State University
Wednesday March 24, 2010
Advances in Power Distribution, Placement and Routing
Chair: Sanghamitra Roy
Co-Chair: Vamsi Srikantham
1:30PM
5A.1
A Negotiated Congestion based Router for Simultaneous Escape Routing
Qiang Ma, Tan Yan, Martin D. F. Wong
University of Illinois at Urbana-Champaign
2:00PM
5A.2
Dynamic Voltage (IR) Drop Analysis and Design Closure: Issues and Challenges
Nithin S K, Gowryshankar Shanmugham, Sreeram Chandrashekhar
Texas Instruments
2:30PM
5A.3
Analog Placement and Global Routing Considering Wiring Symmetry
Yu-Ming Yang and Iris Hui-Ru Jiang
National Chiao Tung University
2:50PM
5A.4
Worst-Case Noise Prediction With Non-zero Current Transition Times for Early Power Distribution System Verification
Peng Du1, Xiang Hu1, Shih-Hung Weng1, Amirali Shayan1, Xiaoming Chen2, A. Ege Engin3, Chung-Kuan Cheng1
1University of California, San Diego, 2Qualcomm Inc., 3San Diego State University
3:10PM
5A.5
Fixed Outline Multi-Bend Bus Driven Floorplanning
Wenxu Sheng1, Sheqin Dong1, Yuliang Wu2, Satoshi Goto3
1Tsinghua University, 2The Chinese University of HongKong, 3WASEDA University
Wednesday March 24, 2010
Aging Analysis & Mitigation
Chair: Srinivas Bodapati
Co-Chair: Keith Bowman
1:30PM
5B.1
Scalable Methods for the Analysis and Optimization of Gate Oxide Breakdown
Jianxin Fang and Sachin Sapatnekar
Department of ECE, University of Minnesota
2:00PM
5B.2
Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration
Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
Osaka University
2:30PM
5B.3
Multi-Corner, Energy-Delay Optimized, NBTI-Aware Flip-Flop Design
Hamed Abrishami, Safar Hatami, Massoud Pedram
University of Southern California
2:50PM
5B.4
Signal Probability Control for Relieving NBTI in SRAM Cells
Yuji Kunitake1, Toshinori Sato2, Hiroto Yasuura1
1Kyushu University, 2Fukuoka University
3:10PM
5B.5
Early-Stage Determination of Current-Density Criticality in Interconnects
Goeran Jerke1 and Jens Lienig2
1Robert Bosch GmbH, Germany, 2Dresden University of Technology, Germany
Wednesday March 24, 2010
Test, Quality, Cost and Debug
Chair: Priyadarsan Patra
Co-Chair: Shankar Hemmady
1:30PM
5C.1
Automated Silicon Debug Data Analysis Techniques for a Hardware Data Acquisition Environment
Yu-Shen Yang1, Brian Keng1, Nicola Nicolici2, Andreas Veneris1, Sean Safarpour3
1University of Toronto, 2McMaster University, 3Vennsa Technologies Inc.
2:00PM
5C.2
Layout-Aware Illinois Scan Design for High Fault Coverage
Shibaji Banerjee1, Jimson mathew1, Dhiraj Pradhan1, Saraju P Mohanty2
1University of Bristol, 2Univ of North Texas, Denton, TX 76203
2:30PM
5C.3
Multi-Degree Smoother for Low Power Consumption in Single and Multiple Scan-Chains BIST
Abdallatif S. Abu-Issa1 and Steven F. Quigley2
1Faculty of Information Technology, Birzeit University, Birzeit, P.O. Box 14, Palestine, 2School of Electronic, Electrical, and Computer Engineering. The University of Birmingham, Birmingham, UK
2:50PM
5C.4
Multiplexed Trace Signal Selection Using Non-Trivial Implication-Based Correlation
Sandesh Prabhakar and Michael Hsiao
Virginia Tech
3:10PM
5C.5
Modeling and Verification of Industrial Flash Memories
Sandip Ray1, Jayanta Bhadra2, Thomas Portlock3, Ronald Syzdek3
1University of Texas at Austin, 2Freescale Semiconductor Inc., 3Freescale Semiconductor Inc
Wednesday March 24, 2010
System-level NoC, SoC and ASIC design
Chair: Makram Mansour
Co-Chair: Sao-Jie Chen
1:30PM
5D.1
Auto-BET-AMS: An Automated Device and Circuit Optimization Platform to Benchmark Emerging Technologies for Performance and Variability using an Analog and Mixed-Signal Design Framework
Angada B. Sachid1, Rajesh A. Thakker1, Chaitanya Sathe2, Maryam Shojaei Baghini1, Dinesh K. Sharma1, V. Ramgopal Rao1, Mahesh B. Patil1
1Department of Electrical Engineering, Indian Institute of Technology Bombay, 2University of Illinois, Urbana-Champaign
2:00PM
5D.2
UC-PHOTON: A Novel Hybrid Photonic Network-on-Chip for Multiple Use-Case Applications
Shirish Bahirat and Sudeep Pasricha
Department of Electrical and Computer Engineering, Colorado State University, Fort Collins, CO 80523-1373
2:30PM
5D.3
Hellfire: A Design Framework for Critical Embedded Systems' Applications
Alexandra Aguiar, Sérgio Johann filho, Felipe Magalhães, Thiago Casagrande, Fabiano Hessel
PUCRS
2:50PM
5D.4
Slack Allocation for Yield Improvement in NoC-based MPSoCs
Brett Meyer1, Adam Hartman2, Don Thomas1
1Carnegie Mellon University, 2Carnegie Mellon Univeristy
3:10PM
5D.5
Power-Yield optimization in MPSoC Task Scheduling under Process Variation
Mahmoud Momtazpour, Esmaeel Sanaei, Maziar Goudarzi
Sharif University of Technology
Wednesday March 24, 2010
Clocking Strategy for Modern Low Power Multi-Core and Structured ASICs
Chair: Baris Taskin
Co-Chair: Mark Young
3:45PM
6A.1
A Revisit to the Primal-Dual Based Clock Skew Scheduling Algorithm
Min Ni1 and Seda Ogrenci Memik2
1Synopsys, Inc., 2EECS Northwestern University
4:15PM
6A.2
Clock Buffer Polarity Assignment Considering Capacitive Load
Jianchao Lu and Baris Taskin
Drexel University
4:45PM
6A.3
A Low Power Clock Network Placement Framework
Dawei Liu, Qiang Zhou, Yongqiang Lv, Jinian Bian
Department of Computer Science and Technology Tsinghua University
5:05PM
6A.4
Clock Routing for Structured ASICs with Via-Configurable Fabrics
Rung-Bin Lin, I-Wei Lee, Wen-Hao Chen
Yuan Ze University
5:25PM
6A.5
Analysis of Power Supply Induced Jitter in Actively De-skewed Multi-Core Systems
Derek Chan and Matthew Guthaus
UC Santa Cruz
Wednesday March 24, 2010
Modeling and Analysis of Temperature and Power
Chair: Murat Becer
Co-Chair: Zhuo Feng
3:45PM
6B.1
Analyzing and Minimizing Effects of Temperature Variation and BTI on Active Leakage Power of Power-Gated Circuits
Abhishek Sinkar and Nam Sung Kim
Univ. of Wisconsin-Madison
4:15PM
6B.2
Signal Processing Methods and Hardware-Structure for On-line Characterization of Thermal Gradients in Many-Core Processors
Minki Cho and Saibal Mukhopadhyay
Georgia Institute of Technology
4:45PM
6B.3
A Convex Optimization Framework for Leakage Aware Thermal Provisioning in 3D Multicore Architectures
Sanghamitra Roy and Koushik Chakraborty
Utah State University
5:05PM
6B.4
Improving the Process Variation Tolerability of Flip-Flops for UDSM Circuit Design
Eun Ju Hwang, Wook Kim, Young Hwan Kim
Pohang University of Science and Technology
5:25PM
6B.5
Interconnect Delay and Slew Metrics Using the Extreme Value Distribution
Zeng Jun-Kuei
National Taiwan University
Wednesday March 24, 2010
Fault Tolerant Design
Chair: Keith Bowman
Co-Chair: Riaz Naseer
3:45PM
6C.1
Design Methodology of Variable Latency Adders with Multistage Function Speculation
yongpan liu, yinan sun, yihao zhu, huazhong yang
Tsinghua univ.
4:15PM
6C.2
Accurate Statistical Soft Error Rate (SSER) Analysis Using A Quasi-Monte Carlo Framework With Quality Cell Models
Yu-Shin Kuo, Huan-Kai Peng, Charles H.-P. Wen
National Chiao Tung University
4:45PM
6C.3
Measurement Circuits for Acquirinng SET Pulse Width Distribution with Sub-FO1-inverter-delay Resolution
Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
Osaka University
5:05PM
6C.4
Design of a Fault-Tolerant Coarse-Grained Reconfigurable Architecture: A Case Study
Syed M. A. H. Jafri1, Stanislaw J. Piestrak2, Olivier Sentieys3, Sebastien Pillement3
1University of Rennes 1, 22300 Lannion, France, 2IRISA/INRIA---University of Rennes 1, 22300 Lannion, France, 3IRISA/INRIA---University of Rennes 1,22300 Lannion, France
5:25PM
6C.5
Comparative Analysis and Study of Metastability on High-Performance Flip-Flops
David Li, Pierce Chuang, Manoj Sachdev
University of Waterloo
Wednesday March 24, 2010
Quality system level design
Chair: Anand Iyer
Co-Chair: He Qian
3:45PM
6D.1
Reliability Analysis of Analog Circuits by Lifetime Yield Prediction Using Worst-Case Distance Degradation Rate
Xin Pan and Helmut Graeb
Institute for Electronic Design Automation, Technische Universitaet Muenchen, Munich, Germany
4:15PM
6D.2
The Compatibility Analysis of Thread Migration and DVFS in Multi-Core Processor
Dongkeun Oh1, Charlie Chen2, Yu Hen Hu1, Nam Sung Kim1
1University of Wisconsin–Madison, 2National Taiwan University
4:45PM
6D.3
Analog Behavioral Modeling Flow using Statistical Learning Method
Hui Li1, Makram Mansour1, Sury Maturi1, Li Wang2
1National Semiconductor, 2University of California, Santa Barbara
5:05PM
6D.4
Coprocessor Design Space Exploration Using High Level Synthesis
Avinash Lakshminarayana, Sumit Ahuja, Sandeep Shukla
Virginia Polytechnic Institute and State University
5:25PM
6D.5
Methodology From Chaos in IC Implementation
Kwangok Jeong and Andrew Kahng
University of California San Diego
