Low Power Low Phase Noise CMOS PLL

Abishek Mann,  Amit Karalkar,  Lili He,  Morris Jones
san jose state university

Abstract

The present research relates to a phase lock loop with low phase noise, low power consumption and less area for implementing on IC. More specifically the present research relates a Phase Lock Loop with a VCO and Phase detector redesigned for low power, low phase noise and less area.