Design tradeoffs of power consumption, speed and robustness exist in high fan-in OR domino gates. In this paper, a novel design combining the modified supply voltage keeper technique and the low body voltage keeper is proposed to address this dilemma. Simulation results show that the proposed technique can improve the overall performance and the high fan-in domino OR logic is taken to a new level of high-speed, low-power and robust operation. Thus, high fan-in domino OR logic may still be employed in the deep submicron technologies where robustness to noise and process variations is becoming an increasingly limiting issue. The significant improvement, however, comes at the cost of additional complexity as multiple supply voltage and bias generators are necessary, as well as a more complex algorithm for determining the optimum set of supply voltage and bias voltage of keeper.