This paper studies multi-core clock distribution using active deskewing methods. We propose an efficient methodology that uses Verilog-A to model PLLs, clock trees and power supply variation in multi-core designs. Using the methodology, we compare four different de-skewing topologies (region-based, linear, ring, and a tree) for nominal performance and robustness to power supply variation. We conclude that under nominal conditions, the ring and line topologies are better with a large number of cores, but, when power supply is considered, the region topology is best.