Chair:  Vinod Viswanath,  Real Intent
Co-Chair: Srini Krishnamoorthy, AMD

10:00AM
1A.1
Concolic Testing of SystemC Designs
Bin Lin¹, Kai Cong², Zhenkun Yang², Zhigang Liao³, Tao Zhan⁴, Christopher Havlicek¹, Fei Xie^1
1Portland State University, ²Intel Corporation, ³Virtual Device Technologies LLC, ⁴Northwestern Polytechnical University

10:20AM
1A.2
A Droop Measurement Built-in Self-Test Circuit for Digital Low-Dropout Regulators
Aydin Dirican, Cagatay Ozmen, Martin Margala
University of Massachusetts Lowell

10:40AM
1A.3
Test Set Identification for Improved Delay Defect Coverage in the Presence of Statistical Delays
Pavan Kumar Javvaji¹, Basim Shanyour², Spyros Tragoudas^1
1Southern Illinois University Carbondale, ²Southern Illinois University- Carbondale

11:00AM
1A.4
Augmenting ESD and EOS Physical Analysis with Per Pin ESD and Leakage DFT
Horaira Abu, Salem Abdennadher, Benoit Provost, Harry Muljono
Intel Corporation

Chair: Rajesh Berigei, MathWorks
Co-Chair: Jingtong Hu, University of Pittsburgh

10:00AM
1B.1
Hybrid-Comp: A Criticality-Aware Compressed Last-Level Cache
Amin Jadidi¹, Mohammad Arjomand², Mahmut Kandemir¹, Chita Das^1
1Pennsylvania State University, ²Georgia Institute of technology

10:20AM
1B.2
Energy-Optimal Dynamic Voltage Scaling in Multicore Platforms with Reconfigurable Power Distribution Network
Juyeon Kim¹ and Taewhan Kim^2
1Samsung Electronics, ²Seoul National University

10:40AM
1B.3
Optimizing Energy in a DRAM based Hybrid Cache
Jiacong He¹ and Joseph Callenes-Sloan^2
1University of Texas at Dallas, ²California Polytechnic State University

11:00AM
1B.4
Program Acceleration Using Nearest Distance Associative Search
Mohsen Imani¹, Daniel Peroni², Tajana Rosing^3
1University of California San Diego, ²University of California at San Diego, ³UCSD

Chair: Shih-Hung Chen, IMEC
Co-Chair: Swaroop Ghosh, Pennsylvania State University

10:00AM
1C.1
Synthesis of Normally-Off Boolean Circuits: An Evolutionary Optimization Approach Utilizing Spintronic Devices
Arman Roohi, Ramtin Zand, Ronald F DeMara
Computer Systems and Architecture Laboratory, Department of EECS, University of Central Florida

10:20AM
1C.2
LUPIS : Latch-Up Based Ultra Efficient Processing-in-Memory System
Joonseop Sim¹, Mohsen Imani¹, Woojin Choi¹, Yeseong Kim², Tajana Rosing^1
1UCSD, ²University of California San Diego

10:40AM
1C.3
Energy efficient neuromorphic processing using spintronic memristive device with dedicated synaptic and neuron terminology
Zoha Pajouhi
Intel Corporation

11:00AM
1C.4
A Bi-Memristor Synapse with Spike-Timing-Dependent Plasticity for On-Chip Learning in Memristive Neuromorphic Systems
Sagarvarma Sayyaparaju, Sherif Amer, Garrett S. Rose
The University of Tennessee, Knoxville

Chair: Srini Krishnamoorthy, AMD
Co-Chair:  Vinod Viswanath,  Real Intent

3:45PM
2A.1
Recognition of Regular Layout Structures
Yu-Cheng Chiang, Shr-Cheng Tsai, Rung-Bin Lin
Yuan Ze University

4:05PM
2A.2
A Simplified Methodology for Complex Analog Module Layout Generation
Pradeep Chawda
Texas Instruments

4:25PM
2A.3
Process Variation Aware D-Flip-Flop Design using Regression Analysis
Shinichi Nishizawa¹ and Hidetoshi Onodera^2
1Saitama University, ²Kyoto University

4:45PM
2A.4
Clock Buffer and Flip-flop Co-optimization for Reducing Peak Current Noise
Joohan Kim¹ and Taewhan Kim^2
1Samsung Electronics, ²Seoul National University

5:05PM
2A.5
Parasitic-Aware gm/ID-Based Many-Objective Analog/RF Circuit Sizing
Tuotian Liao¹ and Lihong Zhang^2
1Memorial University of Newfoundland, ²Memorial University of Newfoundlan

Chair: Rajesh Berigei, MathWorks
Co-Chair: Jingtong Hu, University of Pittsburgh

3:45PM
2B.1
A Loop Structure Optimization targeting High-level Synthesis of Fast Number Theoretic Transform
Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
Waseda University

4:05PM
2B.2
A 4-PAM Interconnect in Network-on-Chip for High-Throughput and Latency-Sensitive Applications
Ahmad Mansour¹, Ahmed Elnaggar¹, Bassma Alabassy², Mostafa Khamis², Ahmed Shalaby^3
1EE Department, Alexandria University, Egypt., ²Mentor Graphics, ³Faculty of Computers and Informatics, Benha University, Egypt

4:25PM
2B.3
Comparative Study and Prediction Modeling of Photonic Ring Network on Chip Architectures
Sara Karimi¹ and Jelena Trajkovic^2
1M.Sc Concordia University, ²Assistant Professor in Concordia University

4:45PM
2B.4
Power and Performance Aware Memory-Controller Voting Mechanism
Milena Vratonjic¹, Harmander Singh², Gautam Kumar³, Roumi Mohamed³, Ashish Bajaj³, Ken Gainey^1
1Qualcomm Atheros, Inc., ²Qualcomm Technologies Inc., ³Qualcomm India Private Limited

5:05PM
2B.5
PDA-HyPAR: Path-Diversity-Aware Hybrid Planar Adaptive Routing Algorithm for 3D NoCs
Jindun Dai¹, Renjie Li², Xin Jiang³, Takahiro Watanabe^4
1Shanghai Jiao Tong University, ²The Graduate School of Information Production and Systems, Waseda University, ³Graduate School of Information Production and Systems, Waseda University, Japan, ⁴The Graduate School of Information, Production and Systems Of Waseda University, Japan

Chair: Swaroop Ghosh, Pennsylvania State University

5:55PM
P1
Network on Interconnect Fabric
Boris Vaisband, Adeel Bajwa, Subramanian Iyer
University of California, Los Angeles

5:55PM
P2
Efficient K Nearest Neighbor Algorithm Implementations for Throughput-Oriented Architectures
Jihyun Ryoo¹, Meena Arunachalam², Rahul Khanna², Mahmut Kandemir^1
1Pennsylvania State University, ²Intel

5:55PM
P3
Body-Biasing Assisted Vmin Optimization for 5nm-Node Multi-Vt FD-SOI 6T-SRAM
Jheng-Yi Chen, Ming-Yu Chang, Shi-Hao Chen, Jia-Wei Lee, Meng-Hsueh Chiang
National Cheng Kung University

5:55PM
P4
Measuring the effectiveness of ISO26262 compliant Self Test Library
Frederico Pratas, Thomas Dedes, Andrew Webber, Majid Bemanian, Itai Yarom
MIPS

5:55PM
P5
An Online Framework for Diagnosis of Multiple Defects in Scan Chains
Sarmad Tanwir¹, Michael Hsiao¹, Loganathan Lingappan^2
1Virginia Tech, ²Intel Corporation

5:55PM
P6
Routing at Compile Time
Chun-Xun Lin, Tsung-Wei Huang, Martin Wong
University of Illinois at Urbana-Champaign

5:55PM
P7
Uncertainty Aware Mapping of Embedded Systems for Reliability, Performance, and Energy
Wenkai Guan, Milad Ghorbani Moghaddam, Cristinel Ababei
Marquette University

5:55PM
P8
On the Write Energy of Non-Volatile Resistive Crossbar Arrays With Selectors
Albert Ciprut and Eby G. Friedman
University of Rochester

5:55PM
P9
A Modified Method of Logical Effort for FinFET Circuits Considering Impact of Fin-Extension Effects
Archana Pandey¹, Pitul Garg², Shobhit Tyagi², Rajeev Ranjan³, Anand Bulusu^2
1Indian Institute of Technology Roorkee, ²IIT Roorkee, ³Samsung Electronics, Republic of Korea

5:55PM
P10
Generic System-Level Modeling and Optimization for Beyond CMOS Device Applications
Victor Huang, Chenyun Pan, Azad Naeemi
Georgia Institute of Technology

5:55PM
P11
Terahertz Travelling Wave Amplifier Design using Ballistic Deflection Transistor
Huan Wang¹, Jean-François Millithaler¹, Ronald Knepper², Martin Margala^1
1University of Massachusetts, ²Boston University

5:55PM
P12
Reliable Memory PUF Design for Low-Power Applications
Mohammad Saber Golanbari, Saman Kiamehr, Rajendra Bishnoi, Mehdi Tahoori
Karlsruhe Institute of Technology

5:55PM
P13
An ESD Transient Clamp with 494 pA Leakage Current in GP 65 nm CMOS Technology
Mahdi Elghazali, Manoj Sachdev, Ajoy Opal
University of Waterloo

5:55PM
P14
Enhancing Circuit Operation using Analog Floating Gates
Ujas Patel¹, Sai Govinda Rao Nimmalapudi¹, Harvey Stiegler¹, Andrew Marshall¹, Keith Jarreau^2
1University of Texas at Dallas, ²Texas Instruments Incorporated

5:55PM
P15
An Automated Flow for Design Validation of Switched Mode Power Supply
Pradeep Chawda¹ and Srikrishna Srinivasan^2
1Texas Instruments, ²Texas Instruments Inc

5:55PM
P16
Dynamic NoC Platform for Varied Application Needs
Sidhartha Sankar Rout¹, Hemanta Kumar Mondal², Rohan Juneja¹, Sri Harsha Gade¹, Sujay Deb^1
1IIIT Delhi, ²University of Southern Brittany, Lab STICC, Lorient, france

Chair:  Vinod Viswanath,  Real Intent
Co-Chair: Srini Krishnamoorthy, AMD

10:00AM
3A.1.1
A Technique to Aggregate Classes of Analog Fault Diagnostic Data Based on Association Rule Mining
Ruslan Dautov¹ and Sergey Mosin^2
1Shenzhen University, ²Kazan Federal University

10:20AM
3A.1.2
Extracting Hardware Assertions Including Word-Level Relations over Multiple Clock Cycles
Mami Miyamoto and Kiyoharu Hamaguchi
Shimane University

Chair: Srini Krishnamoorthy, AMD
Co-Chair:  Vinod Viswanath,  Real Intent

10:40AM
3A.2.1
A Study on NBTI-induced Delay Degradation Considering Stress Frequency Dependence
Zuitoku Shin¹, Shumpei Morita¹, Song Bian¹, Michihiro Shintani², Masayuki Hiromoto¹, Takashi Sato^1
1Kyoto University, ²Nara Institute of Science and Technology

11:00AM
3A.2.2
Verification Methodology to Guarantee Low Routing Resistance to Well Taps
MOHAMMED FAKHRUDDIN, Kuok-Khian Lo, James Karp, Michael Hart, Min-Hsing Chen
Xilinx, Inc.

Chair: Kurt Schwartz, Texas Instruments, Inc
Co-Chair: Jose Pineda de Gyvez, Eindhoven Univ of Technology

10:00AM
3B.1
Ultra-Low Swing CMOS Transceiver for 2.5-D Integrated Systems
Przemyslaw Mroszczyk and Vasilis Pavlidis
The University of Manchester

10:20AM
3B.2
Back-Bias Generator for Post-Fabrication Threshold Voltage Tuning Applications in 22nm FD-SOI Process
Arif Siddiqi, Navneet Jain, Mahbub Rashed
Global Foundries

10:40AM
3B.3
Logic-based Row Redundancy Technique Designed in 7nm FinFET Technology for Embedded SRAMs
Vivek Nautiyal, Nishant Nukala, Fakhruddinali Bohra, Sagar Dwivedi, Jitendra Dasani, Satinderjit Singh, Gaurav Singla, Martin Kinkade Kinkade
ARM

11:00AM
3B.4
A 125mV 2ns-Access-Time 16Kb SRAM Design based on a 6T Hybrid TFET-FinFET Cell
Hassan Afzali-Kusha¹, Alireza Shafaei Bejestan², Massoud Pedram^1
1USC, ²University of Southern California

Chair: Pradeep Chawda, Texas Instruments, Inc
Co-Chair: Ali A. Shahi, Globalfoundaries

10:00AM
3C.1
New AC Resistance Calculation of Printed Spiral Coils for Wireless Power Transfer
Gaorong Qian, Yuhua Cheng, Guoxiong Chen, Gaofeng Wang
Hangzhou Dianzi University

10:20AM
3C.2
An Automated Design Flow for Synthesis of Optimal Multi-layer Multi-shape PCB Coils for Inductive Sensing Applications
Pradeep Chawda
Texas Instruments

10:40AM
3C.3
When "things" get older - Exploring Circuit Aging in IoT Applications
Xinfei Guo, Vaibhav Verma, Patricia Gonzalez-Guerrero, Mircea Stan
University of Virginia

Chair: Aswin Mehta, Texas Instruments, Inc
Co-Chair: Sicheng Li, HPE

11:40AM
4A.1.1
A systematic study of hotspot detection in physical designs using machine learning
Piyush Verma¹, Robert Pack², Sriram Madhavan^2
1Globalfoundries Inc., ²Globalfoundaries

Chair: Sicheng Li, HPE
Co-Chair: Aswin Mehta, Texas Instruments, Inc.

12:00PM
4A.2.1
A Deep Learning Based Approach for Analog Hardware Implementation of Delayed Feedback Reservoir Computing System
Jialing Li, Kangjun Bai, Lingjia Liu, Yang Yi
Virginia Tech

12:20PM
4A.2.2
An Area and Energy Efficient Design of Domain-Wall Memory-Based Deep Convolutional Neural Networks using Stochastic Computing
Xiaolong Ma¹, Yipeng Zhang¹, Geng Yuan¹, Ao Ren¹, Zhe Li¹, Jie Han², Jingtong Hu³, Yanzhi Wang^1
1Syracuse University, ²university of alberta, ³University of Pittsburgh

12:40PM
4A.2.3
A Path to Energy-efficient Spiking Delayed Feedback Reservoir Computing System for Brain-inspired Neuromorphic Processors
Kangjun Bai¹ and Yang Yi^2
1Virginia Tech, ²Department of Electrical and Computer Engineering, Virginia Tech

Chair: Jose Pineda de Gyvez, Eindhoven Univ of Technology
Co-Chair: Raviprakash Rao, Texas Instruments, Inc

11:40AM
4B.1
Low Power Latch Based Design with Smart Retiming
Kamlesh Singh¹, Hailong Jiao², Jos Huisken³, Hamed Fatemi⁴, Josè Pineda de Gyvez^4
1Eindhoven University of Technology (TU/e), ²Peking University Shenzhen Graduate School Shenzhen, China, ³Eindhoven University of Technology, The Netherlands, ⁴NXP Semiconductors, The Netherlands

12:00PM
4B.2
Parallel implementation of finite state machines for reducing the latency of stochastic computing
Cong Ma and David Lilja
University of Minnesota

12:20PM
4B.3
A Post-Silicon Hold Time Closure Technique using Data-Path Tunable-Buffers for Variation-Tolerance in Sub-threshold Designs
Divya Akella Kamakshi¹, Xinfei Guo¹, Harsh Patel¹, Mircea Stan², Benton Calhoun^1
1University of Virginia, ²

12:40PM
4B.4
A Low-Power Configurable Adder for Approximate Applications
Tongxin Yang, Tomoaki Ukezono, Toshinori Sato
Fukuoka University

Chair: Pradeep Chawda, Texas Instruments, Inc
Co-Chair: Ali A. Shahi, Globalfoundaries

11:40AM
4C.1
Mathematical Derivation, Circuits Design and Clinical Experiments of Measuring Blood Flow Volume (BFV) at Arteriovenous Fistula (AVF) of Hemodialysis (HD) Patients Using a Newly-Developed Photoplethysmography (PPG) Sensor
Paul (C.P.) Paul
National Chiao Tsung University

12:00PM
4C.2
A Wireless Multifunctional Monitoring System of Tower Body Running State Based on MEMS Acceleration Sensor
Linxi Dong, Haonan Wang, Gaofeng Wang, Weimin Qiu
Hangzhou Dianzi University

12:20PM
4C.3
Power Management Factors and Techniques for IoT Design Devices
Anupriya Prasad and Pradeep Chawda
Texas instruments

12:40PM
4C.4
Hierarchical Dynamic Goal Management for IoT Systems
Axel Jantsch¹, Arman Anzanpour², Hedyeh Kolerdi¹, Iman Azimi², Lydia Chaido Siafara¹, Amir M. Rahmani³, Nima TaheriNejad¹, Pasi Liljeberg², Nikil Dutt^4
1TU Wien, ²University of Turku, ³University of California Irvine & TU Wien, ⁴UC Irvine

Chair: Sicheng Li, HPE
Co-Chair: Aswin Mehta, Texas Instruments, Inc.

3:40PM
5A.1
Quantized Neural Networks with New Stochastic Multipliers
Bingzhe Li¹, MohammadHassan Najafi¹, Bo Yuan², David Lilja^1
1University of Minnesota-twin cities, ²City University of New York

4:00PM
5A.2
High Performance Training of Deep Neural Networks Using Pipelined Hardware Acceleration and Distributed Memory
Raghav Mehta¹, Yuyang Huang², Mingxi Cheng³, Shrey Bagga⁴, Nishant Mathur⁴, Ji Li⁴, Jeffrey Draper⁵, Shahin Nazarian^4
1Mentor, A Siemens Business, ²NVIDIA, ³Duke University, ⁴University Of Southern California, ⁵Information Sciences Institute

4:20PM
5A.3
Deep Neural Network Acceleration Framework Under Hardware Uncertainty
Mohsen Imani¹, Pushen Wang¹, Tajana Rosing^2
1University of California San Diego, ²UCSD

4:40PM
5A.4
A Hardware-Friendly Algorithm for Scalable Training and Deployment of Dimensionality Reduction Models on FPGA
Mahdi Nazemi¹, Amir Erfan Eshratifar², Massoud Pedram^1
1USC, ²University of Southern California

Chair: Jon Nafziger, Texas Instruments, Inc
Co-Chair: Jie Gu, Northwestern University

3:40PM
5B.1
Securing FPGA-based Obsolete Component Replacement for Legacy Systems
Zhiming Zhang¹, Laurent Njilla², Charles Kamhoua³, Kevin Kwiat², Qiaoyan Yu^1
1University of New Hampshire, ²Cyber Assurance Branch, Air Force Research Laboratory, ³Army Research Laboratory

4:00PM
5B.2
High-Level Synthesis of Key Based Obfuscated RTL Datapaths
Sheikh Ariful Islam and Srinivas Katkoori
University of South Florida

4:20PM
5B.3
Double Error Cellular Automata-Based Error Correction with Skip-mode Compact Syndrome Coding for Resilient PUF Design
Anthony Mattar El Raachini¹, Hussein Alawieh¹, Adam Issa², Zainab Swaidan¹, Rouwaida Kanj¹, Ali Chehab¹, Mazen Saghir^1
1American University of Beirut, ²University of Toronto

4:40PM
5B.4
Design and Evaluation of Physical Unclonable Function for Inorganic Printed Electronics
Ahmet Turan Erozan¹, Mohammad Saber Golanbari¹, Rajendra Bishnoi¹, Jasmin Aghassi-Hagmann², Mehdi Tahoori^1
1Karlsruhe Institute of Technology, ²Karlsruhe Institute of Technology, Offenburg University of Applied Sciences

Chair: Vivek Joshi, Globalfoundaries
Co-Chair: Swatilekha Saha, Cypress

3:40PM
5C.1
Near-Future Traffic Evaluation based Navigation for Automated Driving Vehicles Considering Traffic Uncertainties
Kuen-Wey Lin¹, Masanori Hashimoto², Yih-Lang Li^1
1National Chiao Tung University, ²Osaka University

4:05PM
5C.2
Low cost & power CNN/Deep learning solution for Automated Driving
Mihir Mody, Kumar Desappan, Pramod Swami, Manu Mathew, Soyeb Nagori
Texas Instruments, Inc

4:30PM
5C.3
Resource Constrained Cellular Neural Networks for Real-time Obstacle Detection using FPGAs.
Yiyu Shi¹, Xiaowei Xu², Tianchen Wang¹, Qing Lu^1
1University of Notre Dame, ²Huazhong university of science and techonology