Augmenting ESD and EOS Physical Analysis with Per Pin ESD and Leakage DFT

Horaira Abu, Salem Abdennadher, Benoit Provost, Harry Muljono
Intel Corporation


Based on technical and functional evaluation of high volume products returned from customers, Electrostatic Discharge (ESD) and Electrical Overstress (EOS) induced damages are the two significant causes of customer return in recent times. These customer returns are expected to rise as silicon scales down, as devices are becoming more susceptible to EOS. Concerned by zero defect targets and EOS failure rate from customers, a need to define new test methods and techniques that are able to reproduce EOS failure, improve IC robustness against EOS events and isolate EOS and ESD failures is on the rise. With ESD diodes ubiquitously being used as the protection device for IC Input/Output (I/O) pin, there is a lack of on-die test structures to validate these circuits automatically. This paper proposes two Design for Test (DFT) techniques that can be used to augment physical analysis used to screen EOS and ESD failures.