Logic-based Row Redundancy Technique Designed in 7nm FinFET Technology for Embedded SRAMs

Vivek Nautiyal, Nishant Nukala, Fakhruddinali Bohra, Sagar Dwivedi, Jitendra Dasani, Satinderjit Singh, Gaurav Singla, Martin Kinkade Kinkade


In this paper, a row-redundancy circuit using latches is designed for 7nm FINFET Ultra high density SRAM operating at 1.75 GHz. Input and faulty addresses are compared in parallel to the memory read access operation thus avoiding a major impact on access or address setup time. Latch output data is multiplexed with memory data and the impact on access time is only 7ps at SS/0.675V/m40c corner. Data is written to redundant latches only when address comparison matches. The proposed circuit is implemented with no setup time impact and an overall area overhead of the proposed row redundancy scheme is less than 1%. The area of the proposed flop based row redundancy scheme as compared to a conventional redundancy scheme, is reduced by 45%.