For high-speed digital circuits, the activation of all flip-flops that are used to store data should be strictly synchronized by clock signals delivered through clock networks. However, due to the high frequency of simultaneous switching of clock pins in flip-flops, a high peak power/ground noise (i.e., voltage drop) is induced at the clock boundary. To mitigate the current noise, we employ four different types of hardware component that can implement a set of flip-flops and their driving buffer as a single unit, which was previously used for reducing clock power consumption. (The idea for the generation of the four types of clock boundary component was that one of the two inverters in a driving buffer and one of the two inverters in each of its driven flip-flops can be nullified without altering the circuit functionality.) Consequently, we have a flexibility of selecting (i.e., allocating) clock boundary components in a way to reduce peak current under timing constraint. We formulate the component allocation problem of minimizing peak current into a multi-objective shortest path problem and solve it efficiently using an approximation algorithm. We have implemented our proposed approach and tested it with ISCAS benchmark circuits. The experimental results confirm that our approach is able to reduce the peak current by 27.7%~30.9% on average.