A 4-PAM Interconnect in Network-on-Chip for High-Throughput and Latency-Sensitive Applications

Ahmad Mansour1, Ahmed Elnaggar1, Bassma Alabassy2, Mostafa Khamis2, Ahmed Shalaby3
1EE Department, Alexandria University, Egypt., 2Mentor Graphics, 3Faculty of Computers and Informatics, Benha University, Egypt


In this paper, a network-on-chip four-level pulse amplitude modulation (4-PAM) scheme is proposed to be used for communication within the network itself in MPSoCs. A current-mode based 4-PAM transmitter is used to encode data transactions between neighboring routers. Decoding data streams is done by a flash-ADC based receiver using clocked latched type comparators. Additionally, this scheme is implemented on networks utilizing high-radix routers with a local concentration factor of 2 IPs per node to encode data streams injected into the network at the network interface and decode them at the input port of the router. We also discuss the required modifications to the router architecture in the input port buffers and introduce a two-stage allocation method to resolve conflicts of output port requests which is essential to maintain system stability after saturation by utilizing a fair flow control methodology. This results in a reduction in wiring load for each router which is an added value that facilitates the routing stage. The evaluation is extended to reflect the overall network performance supporting the use of multi-valued logic and estimate the overhead of implementation on area and power budgets.