The degradation of transistors in integrated circuits is known to be dependent on stress frequency in addition to the well-known stress duty cycle. This paper analyzes the impact of frequency dependence of the NBTI degradation on a processor- scale circuit under various workload scenarios by using different levels of available information. A simple estimation for wire switching frequency from duty cycle is also proposed. Using real workloads running on MIPS processor, it is found that frequency dependency of the worst path delay is not large since there are many DC stress components independent of frequency. However, frequency dependency of path delay increases when DC component decreases due to execution of multiple applications.