Chair: Farhang Yazdani, BroadPak
Co-Chair: John Park, Mentor Graphics

10:20AM
1A.1
Hetero2 3D Integration: A Scheme for Optimizing Efficiency/Cost of Chip Multiprocessors
Shivam Priyadarshi¹,  Niket Choudhary¹,  Brandon Dwiel¹,  Ankita Upreti¹,  Eric Rotenberg²,  Rhett Davis³,  Paul Franzon^2
1Graduate Student, North Carolina State University, Raleigh, ²Professor, North Carolina State University, Raleigh, ³Associate Professor, North Carolina State University, Raleigh

10:40AM
1A.2
Effective Thermal Control Techniques for Liquid-Cooled 3D Multi-Core Processors
Yue Hu,  Shaoming Chen,  Lu Peng,  Edward Song,  Jin-Woo Choi
Louisiana State University

11:00AM
1A.3
Reliability-Constrained Die Stacking Order in 3DICs Under Manufacturing Variability
Tuck-Boon Chan,  Andrew B. Kahng,  Jiajia Li
University of California, San Diego

11:20AM
1A.4
Analytical Modeling and Numerical Simulations of Temperature Field in TSV-based 3D ICs
Yuriy Shiyanovskii¹,  Chris Papachristou¹,  Cheng-Wen Wu^2
1Case Western Reserve University, ²National Tsing Hua University / Industrial Technology Research Institute

11:40AM
1A.5
New Electrical Design Verification Approach for 2.5D/3D Package Signal and Power Integrity
Nozad Karim
Amkor Technology

Chair: Riza Naseer, Intel
Co-Chair: Srivinas Bodapati, Intel

10:20AM
1B.1
An Arbitrary Stressed NBTI Compact Model for Analog/Mixed-Signal Reliability Simulations
Jinbo Wan and Hans Kerkhoff
Testable Design and Testing of Integrated Systems Group, University of Twente, Netherlands

10:40AM
1B.2
Impacts of NBTI and PBTI Effects on Ternary CAM
Yen-Han Lee,  Ing-Chao Lin,  Sheng-Wei Wang
National Cheng Kung University, Taiwan

11:00AM
1B.3
On Predicting NBTI-induced Circuit Aging by Isolating Leakage Change
Yinhe Han¹,  Song Jin¹,  Jiebing Qiu¹,  Qiang Xu²,  Xiaowei Li^1
1Institute of Computing Techology, Chinese Academy of Sciences, ²The Chinese University of Hong Kong

11:20AM
1B.4
Aging-aware Timing Analysis Considering Combined Effects of NBTI and PBTI
Saman Kiamehr,  Farshad Firouzi,  Mehdi B. Tahoori
Karlsruhe Institute of Technology (KIT)

11:40AM
1B.5
Flexible Data Allocation for Scratch-pad Memories to Reduce NBTI Effects
Dimitra Papagiannopoulou,  Patipan Prasertsom,  Iris Bahar
Brown University

Chair: Houman Homayoun, University of California San Diego
Co-Chair: Jose Silva Matos, University of Porto, Portugal

10:20AM
1C.1
Runtime 3-D Stacked Cache Management for Chip-Multiprocessors
Jongpil Jung¹,  Kyungsu Kang²,  Giovanni De Micheli²,  Chong-Min Kyung^1
1KAIST, ²EPFL

10:40AM
1C.2
A Co-Synthesis Methodology for Power Delivery and Data Interconnection Networks in 3D ICs
Nishit Kapadia and Sudeep Pasricha
Colorado State University

11:00AM
1C.3
Temperature Aware Thread Migration in 3D Architecture with Stacked DRAM
Dali Zhao¹,  Houman Homayoun²,  Alex V. Veidenbaum^1
1University of California, Irvine, ²George Mason University

11:20AM
1C.4
A System-level Solution for Managing Spatial Temperature Gradients in Thinned 3D ICs
Arunachalam Annamalai,  Raghavan Kumar,  Arunkumar Vijayakumar,  Sandip Kundu
University of Massachusetts Amherst

11:40AM
1C.5
Vertically-Addressed Test Structures (VATS) for 3D IC Variability and Stress Measurements
Conor O'Sullivan,  Peter Levine,  Siddharth Garg
University of Waterloo

Chair: Jose Silva Matos, University of Porto, Portugal
Co-Chair: Rajesh Berigei, Texas Instruments

1:30PM
2A.1
Energy-Aware Coarse-Grained Reconfigurable Architectures using Dynamically Reconfigurable Isolation Cells
Syed M. A. H. Jafri¹,  Ozan Zeki Bag¹,  Ahmed Hemani¹,  Nasim Farahini¹,  Kolin Paul¹,  Juha Plosila²,  Hannu Tenhunen^1
1Royal Institute of Technology (KTH) Sweden, ²University of Turku (UTU) Finland

1:50PM
2A.2
Hybrid CMOS-TFET based Register Files for Energy-Efficient GPGPUs
Zhi Li,  Jingweijia Tan,  Xin Fu
University of Kansas

2:10PM
2A.3
Compiler-assisted Leakage Energy Optimization of Media Applications on Stream Architectures
Shan Cao¹,  Zhaolin Li²,  Zhixiang Chen¹,  Guoyue Jiang¹,  Shaojun Wei^1
1Institute of Microelectronics, Tsinghua University, ²Tsinghua National Laboratory for Information Science and Technology, Research Institute of Information Technology, Tsinghua University

2:30PM
2A.4
On a Rewriting Strategy for Dynamically Managing Power Constraints and Power Dissipation in SoCs
Vinod Viswanath¹,  Rajeev Muralidhar²,  Harinarayanan Seshadri²,  Jacob Abraham^3
1Real Intent Inc., ²Intel Corp., ³University of Texas at Austin

2:50PM
2A.5
Sustainable Dual-Level DVFS-enabled NoC with On-chip Wireless Links
Jacob Murray,  Rajath Hegde,  Teng Lu,  Partha Pande,  Behrooz Shirazi
Washington State University

3:10PM
2A.6
On the Selection of Adder Unit in Energy Efficient Vector Processing
Ivan Ratkovic,  Oscar Palomar,  Milan Stanic,  Osman S. Unsal,  Adrian Cristal,  Mateo Valero
Barcelona Supercomputing Center

Chair: Amin Khajeh Djahromi, Intel
Co-Chair: Krishnan Sundaresan, Oracle America, Inc.

1:30PM
2B.1
Low-Energy Digital Filter Design Based on Controlled Timing Error Acceptance
Ku He,  Andreas Gerstlauer,  Michael Orshansky
The University of Texas at Austin

1:50PM
2B.2
A Novel and Efficient Method for Power Pad Placement Optimization
Ting Yu and Martin. D. F. Wong
UIUC

2:10PM
2B.3
Min-Cut Based Leakage Power Aware Scheduling in High-Level Synthesis
Nan Wang¹,  Song Chen²,  Takeshi Yoshimura^1
1Graduate School of IPS, Waseda University, ²University of Science and Technology of China

2:30PM
2B.4
Hierarchical Dynamic Power Management Using Model-Free Reinforcement Learning
Yanzhi Wang¹,  Maryam Triki²,  Xue Lin¹,  Ahmed Ammari²,  Massoud Pedram^1
1University of Southern California, ²Carthage University

2:50PM
2B.5
Accurate Architecture-level Thermal Analysis Methods for MPSoC with Consideration for Leakage Power Dependence on Temperature
Jiaqi Yan,  Zuying Luo,  Liang Tang
Beijing Normal University, 19 XinJieKouWai Street, Beijing, P.R.CHINA

3:10PM
2B.6
Application-Driven Power Efficient ALU Design Methodology for Modern Microprocessors
Na Gong¹,  Jinhui Wang²,  Ramalingam Sridhar^1
1University at Buffalo, SUNY, ²VLSI and System Lab, Beijing University of Technology

Chair: Paul Tong, Pericom Semiconductor
Co-Chair: Bao Liu, UT San Antonio

1:30PM
2C.1
Low Power and Compact Mixed-Mode Signal Processing Hardware using Spin-Neurons
Mrigank Sharad¹,  Deliang Fan²,  Kaushik Roy^2
1Purdue University, ²Purdue Univeristy

1:50PM
2C.2
System-level Optimization and Benchmarking for InAs Nanowire Based Gate-All-Around Tunneling FETs
Chenyun Pan,  Ahmet Ceyhan,  Azad Naeemi
Georgia Institute of Technology

2:10PM
2C.3
Impact of Conventional and Emerging Interconnects on the Circuit Performance of Various Post-CMOS Devices
Ahmet Ceyhan and Azad Naeemi
Georgia Institute of Technology

2:30PM
2C.4
Reducing IR Drop in 3D Integration to Less Than 1/4 Using Buck Converter on Top Die (BCT) Scheme
Yasuhiro Shinozuka¹,  Hiroshi Fuketa¹,  Koichi Ishida¹,  Futoshi Furuta²,  Kenichi Osada²,  Kenichi Takeda²,  Makoto Takamiya¹,  Takayasu Sakurai^1
1University of Tokyo, ²Association of Super-Advanced Electronics Technologies (ASET)

2:50PM
2C.5
Energy-Efficient Spin-Transfer Torque RAM Cache Exploiting Additional All-Zero-Data Flags
Jinwook Jung,  Yohei Nakata,  Masahiko Yoshimoto,  Hiroshi Kawaguchi
Kobe University

3:10PM
2C.6
Design Of Ultra High Density And Low Power Computational Blocks using Nano-Magnets
Mrigank Sharad,  Karthik Yogendra,  Kon-Woo Kwon,  Kaushik Roy
Purdue University

Chair: Mark Young, Texas Instruments
Co-Chair: Andre Reis, Universidade Federal do Rio Grande do Sul 

3:50PM
3A.1
LMgr: A Low-Memory Global Router with Dynamic Topology Update and Bending-Aware Optimum Path Search
Jingwei Lu¹ and Chiu-Wing Sham^2
1Department of Computer Science and Engineering, University of California, San Diego, ²Department of Electronic and Information Engineering, The Hong Kong Polytechnic University

4:10PM
3A.2
Vision-inspired Global Routing for Enhanced Performance and Reliability
Jun Yong Shin,  Nikil Dutt,  Fadi Kurdahi
UC Irvine

4:30PM
3A.3
Crosstalk Timing Windows Overlap in Statistical Static Timing Analysis
Hanif Fatemi and Peivand Tehrani
Synopsys, Inc.

4:50PM
3A.4
Multi-objective Optimization Algorithm for Efficient Pin-constrained Droplet Routing Technique in Digital Microfluidic Biochip
Soumyajit Chatterjee,  Hafizur Rahaman,  Tuhina Samanta
Bengal Engineering & Science University, Shibpur, Howrah, India

5:10PM
3A.5
Advances in Wire Routing
Martin D.F. Wong
University of Illinois at Urbana-Champaign

Chair: Abhilash Goyal, Oracle
Co-Chair: Riaz Naseer, Intel

3:50PM
3B.1
Effectiveness of Hybrid Recovery Techniques on Parametric Failures
Shrikanth Ganapathy¹,  Ramon Canal¹,  Antonio Gonzalez²,  Antonio Rubio^3
1Department of Computer Architecture, Universitat Politecnica de Catalunya, ²Intel Barcelona Research Center, ³Department of Electronic Engineering, Universitat Politecnica de Catalunya

4:10PM
3B.2
Fast Reliability Exploration for Embedded Processors via High-level Fault Injection
Zheng Wang,  Chao Chen,  Anupam Chattopadhyay
MPSoC Architectures, RWTH-Aachen

4:30PM
3B.3
Analysis and Reliability Test to Improve the Data Retention Performance of EPROM Circuits
Jiyuan Luan and Michael DiVita
Texas Instruments

4:50PM
3B.4
Enabling Sizing for Enhancing the Static Noise Margins
Valeriu Beiu¹,  Azam Beg¹,  Walid Ibrahim¹,  Fekri Kharbash¹,  Massimo Alioto^2
1UAEU, ²U Michigan Ann Arbor

5:10PM
3B.5
SRAM Bit-line Electromigration Mechanism and its Prevention Scheme
Zhong Guan¹,  Malgorzata Marek-Sadowska¹,  Sani Nassif^2
1Dept. of Electrical and Computer Engineering, UC Santa Barbara, ²IBM Austin Research Laboratory

Chair: Masahiro Fujita, University of Tokyo
Co-Chair: Anand Iyer, AMD

3:50PM
3C.1
Cost-driven 3D Design Optimization with Metal Layer Reduction Technique
Qiaosha Zou¹,  Jing Xie²,  Yuan Xie^3
1Pennsylvania State University, ²Penn State University, ³Penn State University and AMD rsearch

4:10PM
3C.2
TSV-aware Topology Generation for 3D Clock Tree Synthesis
Wulong Liu¹,  Haixiao Du¹,  Yu Wang¹,  Yuchuan Ma²,  Yuan Xie³,  Jinguo Quan⁴,  Huazhong Yang^1
1Dept. of E.E., TNList, Tsinghua University, Beijing, China, ²Dept. of C.S., TNList, Tsinghua University, Beijing, China, ³Dept. of CSE, Pennsylvania State Univ., USA, ⁴Graduate School at Shenzhen, Tsinghua University, China

4:30PM
3C.3
Electrical and Thermal Analysis for Design Exchange Formats in Three Dimensional Integrated Circuits
Rishik Bazaz¹,  Jianyong Xie¹,  Madhavan Swaminathan^2
1Student, Georgia Institute of Technology, ²Professor, Fellow IEEE, Georgia Institute of Technology

4:50PM
3C.4
Reliability Consideration with Rectangle- and Double-Signal Through Silicon Vias Insertion in 3D Thermal–Aware Floorplanning
Chih-han Hsu,  Shanq-Jang Ruan,  Ying-Jung Chen,  Tsang-Chi Kan
Department of Electronic Engineering National Taiwan University of Science and Technology, Taipei, Taiwan

5:10PM
3C.5
Configurable Redundant Via-Aware Standard Cell Design Considering Multi-Via Mechanism
Tsang-Chi Kan,  Hung-Ming Hong,  Ying-Jung Chen,  Shanq-Jang Ruan
Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan

Chair: Syed M Alam, Everspin Technologies
Co-Chair: Mark Budnik, Valparaiso University

5:30PM
P.1
A Novel Flow for Reducing Clock Skew Considering NBTI Effect and Process Variations
Jifeng Chen and Mohammad Tehranipoor
University of Connecticut

5:30PM
P.2
Suspicious Timing Error Prediction with In-Cycle Clock Gating
Youhua Shi,  Hiroaki Igarashi,  Nozomu Togawa,  Masao Yanagisawa
Waseda Univ.

5:30PM
P.3
Performance Entitlement by Exploiting Transistor’s BTI Recovery
Senthil Arasu¹,  Mehrdad Nourani¹,  Vijay Reddy²,  John Carulli^3
1Univ. of Texas at Dallas, ²Texas Instruments Inc, Dallas, ³Texas Instruments Inc. Dallas

5:30PM
P.4
Device Design and Analysis of Logic Circuits and SRAMs for Germanium FinFETs on SOI and Bulk Substrates
Vita Pi-Ho Hu,  Ming-Long Fan,  Pin Su,  Ching-Te Chuang
National Chiao Tung University

5:30PM
P.5
A Novel 6T SRAM Cell with Asymmetrically Gate Underlap Engineered FinFETs for Enhanced Read Data Stability and Write Ability
Shairfe Salahuddin,  Hailong Jiao,  Volkan Kursun
Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology

5:30PM
P.6
Canonical Ordering of Instances to Immunize the FPGA Place and Route Flow from ECO-Induced Variance
Avijit Dutta,  Neil Tuttle,  Krishnan Anandh
Cypress Semiconductor Corporation

5:30PM
P.7
Architecture for Monitoring SET Propagation in 16-bit Sklansky Adder
Varadan Savulimedu Veeravalli and Andreas Steininger
Vienna University of Technology

5:30PM
P.8
Application of Six-Sigma DMAIC Methodology in the Evaluation of Test Effectiveness: A Case Study for EDA Tools
Eman El Mandouh
Quality Assurance Manager , Mentor Graphics

5:30PM
P.9
A Low Power Deflection Routing Method for Bufferless NoC
Chung-Kai Hsu¹,  Kun-Lin Tsai²,  Jing-Fu Jheng¹,  Shanq-Jang Ruan¹,  Chung-An Shen^1
1National Taiwan University of Science and Technology, ²Tunghai University

5:30PM
P.10
A 64-core Platform for Biomedical Signal Processing
Jordan Bisasky¹,  Houman Homayoun²,  Farhang Yazdani³,  Tinoosh Mohsenin^1
1Univ of Maryland - BC, ²George Mason University, ³BroadPak

5:30PM
P.11
Improving Timing Error Tolerance without Impact on Chip Area and Power Consumption
Ken Yano,  Takanori Hayashida,  Toshinori Sato
Fukuoka University

5:30PM
P.12
System-Level Modelling of Dynamic Reconfigurable Designs using Functional Programming Abstractions
Bahram Najafi Uchevler¹,  Kjetil Svarstad¹,  Jan Kuper²,  Christiaan Baaij^2
1Department of Electronics and Telecommunication, NTNU, Norway, ²Department of Computer Science, University of Twente

5:30PM
P.13
Design of a 6 Gbps Continuous-Time Adaptive Equalizer Using a Voltage Rectifier Instead of a Power Detector
Krishna Srinivasan and Jonathan Rosenfeld
Intel Corporation

5:30PM
P.14
A Predictable Compact Model for Non-monotonous Vth-Pelgrom Plot of Long Channel Halo-implanted Transistors
Shigetaka Kumashiro
Renesas Electronics Corporation

5:30PM
P.15
Manufacturable Nanometer Designs using Standard Cells with Regular Layout
Kasyab Parmesh Subramaniyan and Per Larsson-Edefors
Chalmers University of Technology

5:30PM
P.16
Fast Analog Design Optimization using Regression-based Modeling and Genetic Algorithm: A Nano-CMOS VCO Case Study
Dhruva Ghai¹,  Saraju Mohanty²,  Garima Thakral^1
1Oriental University, Indore, India, ²University of North Texas, USA

5:30PM
P.17
Low Power Sensor for Temperature Compensation in Molecular Biosensing
Daniela De Venuto
Politecnico di Bari, Italy

5:30PM
P.18
A Power Efficient and Digitally Assisted CMOS Complementary Telescopic Amplifier with Wide Input Common Mode Range
Rishi Todani and Ashis Kumar Mal
National Institute of Technology, Durgapur

Chair: Syed M. Alam, Everspin Technologies
Co-Chair: Dinesh Somasekhar, Intel

10:20AM
4A.1
Peak Power Reduction of a Sensor Network Processor Fabricated With Deeply Depleted Channel Transistors in 65nm Technology
Kentaro Kawakami,  Takeshi Shiro,  Hironobu Yamasaki,  Katsuhiro Yoda,  Hiroaki Fujimoto,  Kenichi Kawasaki,  Yasuhiro Watanabe
Fujitsu Laboratories Ltd.

10:40AM
4A.2
Evaluation of Tunnel FET-based Flip-Flop Designs for Low Power, High Performance Applications
Matthew Cotter,  Huichu Liu,  Suman Datta,  Vijaykrishnan Narayanan
The Pennsylvania State University

11:00AM
4A.3
A Cost-effective 45nm 6T-SRAM Reducing 50mV Vmin and 53% Standby Leakage with multi-Vt Asymmetric Halo MOS and Write Assist Circuitry
Koji Nii¹,  Makoto Yabuuchi¹,  Hidehiro Fujiwara¹,  Yasumasa Tsukamoto¹,  Yuichiro Ishii¹,  Tetsuya Matsumura¹,  Yoshio Matsuda^2
1Renesas Electronics Corporation, ²Kanazawa University

11:20AM
4A.4
CPDI: Cross-Power-Domain Interface Circuit Design in Monolithic 3D Technology
Jing Xie¹,  Yang Du²,  Yuan Xie^3
1The Pennsylvania State University, ²Qualcomm, Inc., ³The Pennsylvania State University and AMD Research

11:40AM
4A.5
Impact of Process Parameter and Supply Voltage Fluctuations on Multi-Threshold-Voltage Seven-Transistor Static Memory Cells
Hong Zhu and Volkan Kursun
Hong Kong University of Science and Technology

Chair: Sreejit Chakravarty, LSI Logic
Co-Chair: Srivatsa Vasudevan, Synopsys

10:20AM
4B.1
Input-Aware Statistical Timing Analysis-Based Delay Test Pattern Generation
Bao Liu and Lu Wang
University of Texas at San Antonio

10:40AM
4B.2
Effect-Cause Intra-Cell Diagnosis at Transistor Level
Zhenzhou Sun¹,  Alberto Bosio²,  Luigi Dilillo³,  Patrick Girard³,  Aida Todri³,  Arnaud Virazel²,  Etienne Auvray^4
1LIRMM - ST, ²LIRMM - UM2, ³LIRMM - CNRS, ⁴ST

11:00AM
4B.3
Framework for Analog Test Coverage
Debesh Bhatta¹,  Ishita Mukhopadhyay²,  Suriyaprakash Natarajan³,  Prashant Goteti³,  Bin Xue^3
1Georgia Institute of Technology, ²Cornell University, ³Intel Corporation

11:20AM
4B.4
Fast FPGA-Based Fault Injection Tool for Embedded Processors
Mohammad Shokrolah Shirazi,  Brendan Morris,  Henry Selvaraj
University of Nevada, Las Vegas

11:40AM
4B.5
Diagnosis of Small Delay Defects Arising Due to Manufacturing Imperfections using Path Delay Measurements
Ahish Mysore Somashekar and Spyros Tragoudas
SIUC

Chair: James Lei, Altera
Co-Chair: Debasish Das, Synopsys

10:20AM
4C.1
Tabu Search Based Cells Placement in Nanofabric Architectures with Restricted Connectivity
Sadiq M. Sait and Abdalrahman M. Arafeh
King Fahd University of Petroleum & Minerals

10:40AM
4C.2
Relocatable and Resizable SRAM Synthesis for Via Configurable Structured ASIC
Hsin-Hung Liu,  Rung-Bin Lin,  I-Lun Tseng
Yuan Ze University

11:00AM
4C.3
Cost-Efficient Scheduling in High-Level Synthesis for Soft-Error Vulnerability Mitigation
Yuko Hara-Azumi¹ and Hiroyuki Tomiyama^2
1Nara Institute of Science and Technology, ²Ritsumeikan University

11:20AM
4C.4
Analysis of Very Large Resistive Networks Using Low Distortion Embedding
Sandeep Koranne
Mentor Graphics Corporation

11:40AM
4C.5
Efficient Translation Validation of High-Level Synthesis
Tun Li,  Yang Guo,  Wanwei Liu,  Chiyuan Ma
NUDT

Chair: Makram Mansour, Texas Instruments
Co-Chair: Sudeep Pasricha, Colorado State University

1:30PM
5A.1
Performance and Cache Access Time of SRAM-eDRAM Hybrid Caches Considering Wire Delay
Young-Ho Gong,  Hyung Beom Jang,  Sung Woo Chung
Department of Computer and Radio Communication Engineering, Korea University

1:50PM
5A.2
Increasing the Security Level of Analog IPs by Using a Dedicated Vulnerability Analysis Methodology
Noemie Beringuier-Boher¹,  David Hely²,  Vincent Beroulle²,  Joel Damiens³,  Philippe Candelier^3
1Grenoble-INP LCIS and STMicroelectronics, ²Grenoble-INP LCIS, ³STMicroelectronics

2:10PM
5A.3
High-speed DFG-level SEU Vulnerability Analysis for Applying Selective TMR to Resource-Constrained CGRA
Takashi Imagawa,  Hiroshi Tsutsui,  Hiroyuki Ochi,  Takashi Sato
Kyoto University

2:30PM
5A.4
Geostatistics Inspired Fast Layout Optimization of Nanoscale CMOS Phase Locked Loop
Oghenekarho Okobiah,  Saraju Mohanty,  Elias Kougianos
University of North Texas, Denton

2:50PM
5A.5
Performance Validation Through Implicit Removal of Infeasible Paths of the Behavioral Description
Dheepakkumaran Jayaraman and Spyros Tragoudas
Southern Illinois University Carbondale

3:10PM
5A.6
Early System Level Modeling of Real-time Applications on Embedded Platforms
Richard Lee¹,  Karim Abdel-Khalek¹,  Frederic Risacher²,  Samar Abdi^1
1Concordia University, ²Research In Motion

Chair: Mustafa Yelten, Intel
Co-Chair: Rajan Beera, Texas Instruments

1:30PM
5B.1
SUALD: Spacing Uniformity-Aware Layout Decomposition in Triple Patterning Lithography
Zihao Chen¹,  Hailong Yao²,  Yici Cai^2
1Tsinghua University, China, and Department of Microelectronics, Peking University, Beijing 100871, China, ²Tsinghua University, China

1:50PM
5B.2
Stochastic Behavioral Modeling of Analog/Mixed-Signal Circuits by Maximizing Entropy
Rahul Krishnan¹,  Wei Wu¹,  Fang Gong¹,  Lei He^2
1Student Member, IEEE, ²Senior Member, IEEE

2:10PM
5B.3
Analysis, Modeling and Silicon Correlation of Low-voltage Flop Data Retention in 28nm Process Technology
Animesh Datta,  Mohamed Abu-Rahma,  Sachin Dasnurkar,  Hadi Rasouli,  Sean Tamjidi,  Ming Cai,  Samit Sengupta,  PR Chidambaram,  Raghavan Thirumala,  Nikhil Kulkarni,  Prasanna Seeram,  Prasad Bhadri,  Prayag Patel,  Sei Seung Yoon,  Esin Terzioglu
Qualcomm

2:30PM
5B.4
A Comparator Energy Model Considering Shallow Trench Isolation Stress by Geometric Programming
Gong Chen¹,  Yu Zhang¹,  Bo Yang²,  Qing Dong¹,  Shigetoshi Nakatake^1
1The University of Kitakyushu, ²Design Algorithm Laboratory, Inc.

2:50PM
5B.5
Wire Delay Variability in Nanoscale Technology and Its Impact on Physical Design
Sani Nassif,  Gi-Joon Nam,  Shayak Banerjee
IBM Research

3:10PM
5B.6
Multi-trap RTN Parameter Extraction based on Bayesian Inference
Hiromitsu Awano,  Hiroshi Tsutsui,  Hiroyuki Ochi,  Takashi Sato
Kyoto University

Chair: Bin Wu, AMD
Co-Chair: Amir Ajami, Synopsys

1:30PM
5C.1
VERVE: A Framework for Variation-Aware Energy Efficient Synthesis of NoC-based MPSoCs with Voltage islands
Nishit Kapadia and Sudeep Pasricha
Colorado State University

1:50PM
5C.2
A Virtualization Approach for MIPS-based MPSoCs
Alexandra Aguiar,  Carlos Moratelli,  Marcos Sartori,  Fabiano Hessel
PUCRS

2:10PM
5C.3
Thermal-Aware Semi-Dynamic Power Management for Multicore Systems with Energy Harvesting
Yi Xiang and Sudeep Pasricha
Colorado State University

2:30PM
5C.4
On the Interactions Between Real-Time Scheduling and Inter-thread Cache Interferences for Multicore Processors
Yiqiang Ding and Wei Zhang
Virginia Commonwealth University

2:50PM
5C.5
Resource Allocation and Consolidation in a Multi-Core Server Cluster Using a Markov Decision Process Model
Yanzhi Wang,  Shuang Chen,  Hadi Goudarzi,  Massoud Pedram
University of Southern California

3:10PM
5C.6
Reliability-Aware and Energy-Efficient Synthesis of NoC based MPSoCs
Yong Zou and Sudeep Pasricha
Mr.

Chair: Srini Krishnamoorthy, AMD
Co-Chair: Vamsi Srikantam, Applied Micro

3:50PM
6A.1
CMOS Inverter Delay Model Based on DC Transfer Curve for Slow Input
Felipe Marranghello,  André Reis,  Renato Ribas
UFRGS

4:10PM
6A.2
RF Passive Device Modeling and Characterization in 65nm CMOS Technology
Errikos Lourandakis,  Stefanos Stefanou,  Konstantinos Nikellis,  Sotiris Bantas
Helic Inc.

4:30PM
6A.3
An Efficient Method for ECSM Characterization of CMOS Inverter in Nanometer Range Technologies
Baljit Kaur¹,  Sandeep Miryala²,  Sanjeev Kumar Manhas¹,  Anand Bulusu^1
1Indian Institute of Technology, Roorkee,India, ²politecnico di torino, torino

4:50PM
6A.4
Power Integrity Analysis and Discrete Optimization of Decoupling Capacitors on High Speed Power Planes by Particle Swarm Optimization
Jai Narayan Tripathi¹,  Raj Kumar Nagpal²,  Nitin Kumar Chhabra²,  Rakesh Malik²,  Jayanta Mukherjee¹,  Prakash R. Apte^1
1IIT Bombay, ²STMicroelectronics Pvt. Ltd.

5:10PM
6A.5
A Method to Determine the Sensitization Probability of a Non-Robustly Testable Path
Dheepakkumaran Jayaraman¹ and Spyros Tragoudas^2
1Nvidia Corporation, ²Southern Illinois University, Carbondale

Chair: Dinesh Somasekhar, Intel
Co-Chair: Amin Khajeh Djahromi, Intel

3:50PM
6B.1
A Power-Efficient On-Chip Linear Regulator Assisted by Switched Capacitors for Fast Transient Regulation
Suming Lai and Peng Li
Texas A&M University

4:10PM
6B.2
A Versatile Rail to Rail Current Mode Instrumentation Amplifier with an Embedded Band-pass Filter for Bio-potential Signal Conditioning
Anvesha Amaravati and Maryam Shojaei Baghini
IIT-Bombay

4:30PM
6B.3
A 0.2nJ/sample 0.01mm2 Ring Oscillator Based Temperature Sensor for On-Chip Thermal Management
Nicolo Testi and Yang Xu
ECE Department, Illinois Institute of Technology

4:50PM
6B.4
Analysis and Comparison of XOR Cell Structures for Low Voltage Circuit Design
Shinichi Nishizawa,  Tohru Ishihara,  Hidetoshi Onodera
Kyoto University

5:10PM
6B.5
A CMOS High Dimming Ratio Power-LED Driver with a Preloading Inductor Current Method
Kwang Yoon and Keon Lee
Inha University

Chair: Mustafa Yelten, Intel
Co-Chair: Srivinas Bodapati, Intel

3:50PM
6C.1
Protection of Muller-Pipelines from Transient Faults
Syed Rameez Naqvi,  Jakob Lechner,  Andreas Steininger
Embedded Computing Systems, Vienna University of Technology, Vienna, Austria

4:10PM
6C.2
Minimizing Simultaneous Switching Noise at Reduced Power with Constant-Voltage Power Transmission Lines for High-Speed Signaling
Satyanarayana Telikepalli,  Madhavan Swaminathan,  David Keezer
Dept. of Electrical & Computer Engineering, Georgia Institute of Technology

4:30PM
6C.3
Reliable Express-Virtual-Channel-based Network-on-Chip under the Impact of Technology Scaling
Xin Fu¹,  Tao Li²,  Jose Fortes^2
1University of Kansas, ²University of Florida

4:50PM
6C.4
Clustering Techniques and Statistical Fault Injection for Selective Mitigation of SEUs in Flip-Flops
Adrian Evans¹,  Michael Nicolaidis²,  Shi-Jie Wen³,  Thiago Assis^4
1iRoC Technologies, ²Institut National Polytechnique de Grenoble, ³Cisco Systems, ⁴Vanderbilt University

5:10PM
6C.5
Easy-to-Build Arbiter Physical Unclonable Function with Enhanced Challenge/Response Set
Dinesh Ganta and Leyla Nazhandali
Virginia Tech