Negative bias temperature instability (NBTI) has become a serious concern for the lifetime reliability of integrated circuits. On-line aging prediction is a promising way to prevent NBTI-induced circuit failure. However, the ever-increasing parameter variations, design complexity and area overhead degrade the effectiveness of such delay detection-based scheme. In this paper, we propose to use the isolated leakage change in critical path from full-chip leakage measurement result to predict NBTI-induced circuit aging. The chip-level leakage changes under a set of measurement vectors are firstly formulated as an equation set. Solving this equation set can obtain leakage changes in the gates along the critical path. Then, we predict delay degradation on arbitrary critical path based on the correlation between leakage change and delay increase. Our scheme is immune to the runtime noise and accommodates process variation by increasing measurement time overhead. Experimental results demonstrate that our scheme can effectively predict NBTI-induced circuit aging with acceptable accuracy loss.