This work presents a novel approach to estimate the CMOS inverter delay. The proposed model uses the DC transfer curve in order to predict the inverter behavior for a slow input rather than estimating the discharge time. Moreover, the only required empirical parameters are those used to calibrate the transistor model. Results are on very good agreement with HSPICE simulations based on BSIM4 model over a wide range of input slopes and output loads. Comparisons with previously published works show that such new model offers improved modeling with good trade-off between simplicity and accuracy. The average error is near 3% and the worst case error is smaller than 10%.