The mature electronic design automation (EDA) tools and well-defined abstraction-levels for digital circuits have almost automated the digital design process. However, analog circuit design and optimization is still not automated. Custom design of analog circuits and slow analog in SPICE has always needed maximum efforts, skills, design cycle time. This paper presents a novel design flow for constrained optimization of nano-CMOS analog circuits. The proposed analog design flow combines polynomial-regression based models and genetic algorithm for fast optimization. For evaluating the effectiveness of the proposed design flow, power minimization in a 50nm CMOS based current-starved voltage-controlled oscillator (VCO) is carried out, while treating oscillation frequency as a performance constraint. Accurate polynomial-regression based models are developed for power and frequency of the VCO. The goodness-of-fit of the models is evaluated using SSE, RMSE and R-squared. Using these models, we form a constrained optimization problem which is solved using genetic algorithm. The flow achieved 21.67% power savings, with a constraint of frequency >= 100 MHz. To the best of the authors’ knowledge, this is the first study which approaches a VCO design problem as a mathematical constrained optimization involving the usage of regression based modeling and genetic algorithm.