The ON/OFF current and input capacitance of InAs nanowire based gate-all-around (GAA) tunnel FETs are modeled. Based on the device- and system-level models, optimization has been done and comparison has been made between TFETs and CMOS devices under different constraints for both single- and multi-core processors. Several performance metrics have been analyzed, which shows that optimal numbers of cores, power density and die size area exist for maximizing various design targets. TFETs have excellent performance at the low power density range due to the low supply voltage. The limitations of the interconnection and large leakage current at high supply voltage restrict the driving current, leading a lower performance of the TFETs at a high power density and a large core size compared with CMOS. Depending on different design constraints, parallelisms and process variations, optimal design points can be found to maximize various performance metrics including chip throughput and energy × execution time, which is vital to effectively understand and utilize the advantage of the TFETs.