As we enter the deep submicron era, transistors are increasingly added to chips, causing the chips to become hotter in a non-uniform manner. This is due to different processing tasks in different parts of the chips. This thermal gradient also causes a great number of problems such as the reduction in reliability of chips and interconnects due to electromigration, and system performance degradation because of increased delay and lowered clock frequencies. Since these thermal issues exist, interconnect routing, especially global routing, should be performed to consider the temperature distribution of substrates and the actual delay of interconnects. In this paper, we propose a global routing method based on image processing and computer vision techniques in which the probability of chip failure due to interconnect failure is reduced, and performance degradation from increased delay is also prevented. We observed that our method reduced the number of grids in hot regions by up to 50 % when compared with a conventional router, while maintaining the delay of interconnects as small as possible.