We propose a new test array architecture---vertically-addressed test structures (VATS)---to experimentally characterize the within-tier and tier-to-tier process variations and through-silicon via (TSV) induced stress in 3D integrated circuits (ICs). The proposed VATS architecture utilizes the benefits of 3D integration to simultaneously provide high density, low I/O pin utilization, and high fidelity. A test chip featuring eight VATS arrays (>15,000 active devices) has been designed and fabricated in a two-tier, 130-nm 3D IC technology. Simulation results highlight the advantages of the proposed VATS architecture compared to conventional 2D test arrays. We also propose a radial filtering scheme to discriminate between process variations and the impact of TSV-induced stress in 3D ICs.