Conventional Static Random Access Memory (SRAM) cells suffer from an intrinsic data instability problem due to directly-accessed data storage nodes during a read operation. Noise margins of memory cells further shrink with increasing variability and decreasing supply voltage in scaled CMOS technologies. A selected set of novel seven-transistor (7T) and conventional six-transistor (6T) multi-threshold-voltage memory circuits are characterized for data stability, write margin, and idle mode leakage currents with an equal area constraint under parameter variations in this paper. The mean of the statistical read static noise margin distribution is enhanced by up to 2.4X and the mean of the statistical array leakage power consumption distribution is reduced by up to 82% with the triple-threshold-voltage 7T SRAM cells as compared to the traditional 6T SRAM circuits in a UMC 80nm CMOS technology.