Rapid silicon parasitics extraction is discussed in this work based on passive devices fabricated in a 65 nm CMOS process with M1–M9 copper metal layers and one aluminum metal layer AP. Capacitance extraction for overlapping microstrips and shielded microstrip structures is investigated. Individual capacitances are modeled in terms of area and fringe components either between microstrips or between microstrips and silicon substrate. Good correlation to silicon data is achieved for the fabricated test structures. The validity of the proposed model is also investigated for complex passive devices such as inductors and interdigitated capacitors. Device metrics for both type of passive devices are investigated and compared to measured silicon data. Good agreement is achieved in all cases proving the accuracy of the proposed modeling approach.