Chair: Srinivas Bodapati
Co-Chair: Hamid Mahmoodi

10:30AM
1A.1
Small Embeddable NBTI Sensors (SENS) for Tracking On-Chip Performance Decay
Adam Cabe,  Zhenyu Qi,  Stuart Wooters,  Travis Blalock,  Mircea Stan
University of Virginia

11:00AM
1A.2
An Unified FinFET Reliability Model Including High K Gate Stack Dynamic Threshold Voltage, Hot Carrier Injection, and Negative Bias Temperature Instability
Chenyue Ma¹,  Bo Li²,  Lining Zhang¹,  Jin He¹,  Xing Zhang¹,  Xinnan Lin^2
1TSRC, Key Laboratory of Microelectronic Devices and Circuits of Ministry of Education, Institute of Microelectronics, EECS, Peking University, Beijing, P.R.China, ²The Micro- & Nano Electronic Device and Integrated Technology Group, The Key Laboratory of Integrated Microsystems, Shenzhen Graduate School of Peking University, Shenzhen, P. R .China

11:20AM
1A.3
NBTI-Aware Statistical Circuit Delay Assessment
Balaji Vaidyanathan¹,  Anthony Oates¹,  Yuan Xie²,  Yu Wang^3
1TSMC, ²Penn State University, ³Tsinghua University

11:40AM
1A.4
On the efficacy of Input Vector Control to mitigate NBTI effects and leakage power
Yu Wang¹,  Xiaoming Chen¹,  Wenping Wang²,  Varsha Balakrishnan²,  Yu Cao²,  Yuan Xie³,  Huazhong Yang^1
1Tsinghua Univ., ²Arizona State Univ., ³Penn. State Univ.

Chair: Nanda Gopal
Co-Chair: Miroslav Velev

10:30AM
1B.1
Power & Variability Test Chip Architecture and 45nm-Generation Silicon-Based Analysis for Robust, Power-Aware SoC Design
Ramnath Venkatraman,  Ruggero Castagnetti,  Andres Teene,  Benjamin Mbouombouo,  Shiva Ramesh
LSI Corporation

11:00AM
1B.2
On-Chip Dynamic Worst-Case Crosstalk Pattern Detection and Elimination for Bus-based Macro-cell designs
Hariharan Sankaran and Srinivas Katkoori
University of South Florida

11:20AM
1B.3
Worst Case Timing Jitter and Amplitude Noise in Differential Signaling
Wei Yao,  Yiyu Shi,  Lei He,  Sudhakar Pamarti
UCLA

11:40AM
1B.4
A PVT Aware Accurate Statistical Logic Library for High-$\kappa$ Metal-Gate Nano-CMOS
Dhruva Ghai¹,  Saraju Mohanty¹,  Elias Kougianos¹,  Priyadarsan Patra^2
1University of North Texas, ²Intel Corporation

Chair: James Lei
Co-Chair: Masahiro Fujita

10:30AM
1C.1
A General Piece-wise Nonlinear Library Modeling Format and Size Reduction Technique for Gate-level Timing, SI, Power, and Variation Analysis
Xin Wang,  Alireza Kasnavi,  Harold Levy
Synopsys Inc

11:00AM
1C.2
Leakage Optimization Using Transistor-Level Dual Threshold Voltage Cell Library
Lin Yuan¹,  Chandra Sekhar²,  Gang Qu^3
1Synopsys Inc., ²Cisco Corp., ³Univ. of Maryland

11:20AM
1C.3
Accurate Closed-form Parameterized Block-based Statistical Timing Analysis Applying Skew-normal Distribution
Chun-Yu Chuang and Wai-Kei Mak
Department of Computer Science, National Tsing Hua University

11:40AM
1C.4
Characterization of Sequential Cells for Constraint Sensitivities
Savithri Sundareswaran¹,  Jacob Abraham²,  Rajendran Panda¹,  Yun Zhang¹,  Amit Mittal^1
1Freescale, ²The Univ. of Texas at Austin

Chair: Paul Tong
Co-Chair: Bao Liu

10:30AM
1D.1
PETE: A Device/Circuit Analysis Framework for Evaluation and Comparison of Charge Based Emerging Devices
Charles Augustine¹,  Arijit Raychowdhury²,  Kaushik Roy^1
1Purdue University, ²Intel

11:00AM
1D.2
Architecture Design Exploration of Three-Dimensional (3D) Integrated DRAM
Rakesh Anigundi¹,  Hongbin Sun²,  James Lu¹,  Ken Rose¹,  Tong Zhang^1
1Rensselaer Polytechnic Institute, ²Xi'an Jiaotong University

11:20AM
1D.3
Accurate Buffer Modeling with Slew Propagation in Subthreshold Circuits
Jeremy Tolbert and Saibal Mukhopadhyay
Georgia Institute of Technology

11:40AM
1D.4
Robust Differential Asynchronous Nanoelectronic Circuits
Bao Liu
UTSA

Chair: David pan
Co-Chair: Keith Bowman

1:30PM
2A.1
An enhanced topology for reliability of a high performance 3.3V I/O buffer in a single-well bulk CMOS 1.8v-oxide low voltage process
Karthik Rajagopal,  Aatmesh Aatmesh,  Vinod Menezes
Texas Instruments

2:00PM
2A.2
The Design of a Low-Power High-Speed Current Comparator in 0.35-µm CMOS Technology
Soheil Ziabakhsh¹,  Hossein Alavi-rad¹,  Mohammad Alavi-rad²,  Mohammad Mortazavi^2
1Guilan University, ²Sharif University of Technology

2:20PM
2A.3
Comparison of Supply Noise and Substrate Noise Reduction in SiGe BiCMOS and FDSOI Processes
Wai Leng Cheong,  Brian Owens,  HuiEn Pham,  Christopher Hanken,  Jim Le,  Terri Fiez,  Kartikeya Mayaram
Oregon State University

2:40PM
2A.4
An Effective Staggered-Phase Damping Technique for Suppressing Power-Gating Resonance Noise during Mode Transition
Charbel Akl¹,  Rafic Ayoubi²,  Magdy Bayoumi^1
1University of Louisiana at Lafayette, ²University of Balamand

Chair: Hai (Helen) Li
Co-Chair: Bao Liu

1:30PM
2B.1
Design and Application of Multi-Modal Power-Gating Structures
Ehsan Pakbaznia and Massoud Pedram
University of Southern California

2:00PM
2B.2
Revisiting the Linear Programming Framework for Leakage Power vs. Performance Optimization
Kwangok Jeong¹,  Andrew B. Kahng²,  Hailong Yao^3
1ECE Department, University of California at San Diego, ²CSE and ECE Departments, University of California at San Diego, ³CSE Department, University of California at San Diego

2:20PM
2B.3
Parameter Tuning in SVM-Based Power Macro-Modeling
Antonio Gusmao,  L. Miguel Silveira,  Jose Monteiro
INESC-ID / IST - TU Lisbon

2:40PM
2B.4
Performance-Energy Tradeoffs in Reliable NoCs
Ying-Cherng Lan,  Michael Chin Chen,  Wei-De Chen,  Sao-Jie Chen
National Taiwan University

Chair: Saraju Mohanty
Co-Chair: Bhadra Jay

1:30PM
2C.1
3D-GCP: An Analytical Model for the Impact of Process Variations on the Critical Path Delay Distribution of 3D ICs
Siddharth Garg and Diana Marculescu
Carnegie Mellon University

2:00PM
2C.2
Control of Design Specific Variation in Etch-Assisted Via Pattern Transfer by Means of Full-Chip Simulation
Valeriy Sukharev¹,  Armen Kteyan¹,  Ara Markosian¹,  Jun-Ho Choy¹,  Nikolay Khachatryan¹,  Henrik Hovsepyan¹,  Hasmik Lazaryan¹,  Seiji Onoue²,  Takuo Kikuchi²,  Tetsuya Kamigaki^2
1Mentor Graphics Corporation, ²Toshiba Corporation

2:20PM
2C.3
New Subthreshold Design Concepts in 65nm CMOS Technology
Farshad Moradi¹,  Dag Wisland¹,  Hamid Mahmoodi²,  Ali Peiravi^3
1University of Oslo, ²San Francisco State University, ³Ferdowsi University of Mashhad

2:40PM
2C.4
On-Chip Transistor Characterization Arrays with Digital Interfaces for Variability Characterization
Simeon Realov and Kenneth Shepard
Columbia University

Chair: Anand Iyer
Co-Chair: Hao Li

1:30PM
2D.1
Variability-Aware Optimization of Nano-CMOS Active Pixel Sensors using Design and Analysis of Monte Carlo Experiments
Dhruva Ghai,  Saraju Mohanty,  Elias Kougianos
University of North Texas

1:34PM
2D.2
Yield Evaluation of Analog Placement with Arbitrary Capacitor Ratio
Chen Jwu-E¹,  Luo Pei-Wen²,  Wey Chin-Long^1
1Department of Electrical Engineering, National Central University, Jhongli, Taoyuan, Taiwan, ROC., ²SoC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan, ROC.

1:38PM
2D.3
Analysis of Performance and Reliability Trade-Off in Dummy Pattern Design for 32-nm Technology
Aditya Karmarkar¹,  Xiaopeng Xu²,  Victor Moroz²,  Greg Rollins²,  Xiao Lin^2
1Synopsys (India) Private Limited, Hyderabad, Andhra Pradesh, India, ²Synopsys, Inc., Mountain View, CA, USA

1:42PM
2D.4
Statistical Yield Analysis of Silicon-On-Insulator Embedded DRAM
Rouwaida Kanj
IBM Austin Research labs

1:46PM
2D.5
Effect of Regularity-Enhanced Layout on Printability and Circuit Performance of Standard Cells
Hiroki SUNAGAWA¹,  Haruhiko TERADA¹,  Akira TSUCHIYA¹,  Kazutoshi KOBAYASHI¹,  Hidetoshi ONODERA^2
1Department of Communications and Computer Engineering, Kyoto University., ²Department of Communications and Computer Engineering, Kyoto University. JST, CREST

1:50PM
2D.6
Trading off higher execution latency for increased reliability in tile-based massive multi-core architectures
Enric Musoll
ConSentry Networks

1:54PM
2D.7
A Simulation-Based Strategy used in Electrical Design for Reliability
Yan Liu,  Scott Hareland,  Donald Hall,  Bill Wold,  Roger Hubing,  Robert Mehregan,  Ronen Malka,  Manish Sharma,  Tom Lane
Medtronic, Inc.

1:48PM
2D.8
Estimation and Optimization of Reliability of Noisy Digital Circuits
Satish Sivaswamy,  Kia Bazargan,  Marc Riedel
University of Minnesota

2:02PM
2D.9
Combinational Logic SER Estimation with the Presence of Re-convergence
Liu Biwei
National University of Defense Technology

2:06PM
2D.10
Effect of NDD Dosage on Hot-Carrier Reliability in DMOS Transistors
Jone F. Chen¹,  Kuen-Shiuan Tian¹,  Shiang-Yu Chen¹,  Kuo-Ming Wu²,  C. M. Liu^2
1National Cheng Kung University, ²Taiwan Semiconductor Manufacturing Company

2:10PM
2D.11
Side Channel Aware Leakage Management in Nano-scale Cryptosystem-on-Chip (CoC)
Amirali Khatib Zadeh and Catherine Gebotys
University of Waterloo

2:14PM
2D.12
A New Approach to Detect Logic Soft Errors in Digital Circuits
Hai YU,  Michael Nicolaidis,  Lorena Anghel
TIMA

2:18PM
2D.13
An Efficient Approach to SiP Design Integration
Meng-Syue Chan,  Chun-Yao Wang,  Yung-Chih Chen
National Tsing Hua University

2:22PM
2D.14
A New Low Power Test Pattern Generator Using a Variable-Length Ring Counter
Bin Zhou¹,  Yi-zheng Ye¹,  Zhao-lin Li²,  Xin-chun Wu^1
1Microelectronics Center,Harbin Institute of Technology, ²Tsinghua University

2:26PM
2D.15
A Case Study on Logic Diagnosis for System-on-Chip
Youssef Benabboud¹,  Alberto Bosio¹,  Patrick Girard¹,  Serge Pravossoudovitch¹,  Arnaud Virazel¹,  Laroussi Bouzaida²,  Isabelle Izaute^2
1LIRMM - UM2-CNRS, ²STMICROELECTRONICS

2:30PM
2D.16
Proactive Management of X’s in Scan Chains for Compression
Anshuman Chandra,  Yasunari Kanzawa,  Rohit Kapur
Synopsys

2:34PM
2D.17
A Built-In Self-Calibration Scheme for Pipelined ADCs
Hsiu-Ming (Sherman) Chang¹,  Kuan-Yu Lin²,  Chin-Hsuan Chen¹,  Kwang-Ting (Tim) Cheng^1
1ECE, UCSB, U.S.A., ²ITRI, Taiwan

2:38PM
2D.18
A geometric approach to register transfer level satisfiability
Héctor Navarro¹,  Saeid Nooshabadi²,  Juan A. Montiel-Nelson¹,  Víctor Navarro-Botello¹,  J. Sosa¹,  José C. García^1
1Institute for Applied Microelectronics, Univ. of Las Palmas de Gran Canaria, Spain, ²Gwangju Institute of Science and Technology, Republic of Korea

2:42PM
2D.19
Efficient Diagnosis Algorithms for Drowsy SRAMs
Bing-Wei Huang and Jin-Fu Li
National Central University

2:46PM
2D.20
Incremental Power Optimization for Multiple Supply Voltage Design
Yuchun Ma,  Xiang Qiu,  Xiangqing He,  Xianlong Hong
Tsinghua Univ.

2:50PM
2D.21
IP Protection Platform Based on Watermarking Technique
Yun Du,  Yangshuo Ding,  Zhiqiang Gao,  Yujie Chen
Tsinghua University

2:54PM
2D.22
Statistical Static Performance Analysis of Asynchronous Circuits Considering Process Variation
Mohsen Raji,  Behnam Ghvavami,  Hossein Pedram
Amirkabir Univerity of technology

2:58PM
2D.23
A Software Pipelining Algorithm in High-Level Synthesis for FPGA Architectures
Lei Gao¹,  David Zaretsky²,  Gaurav Mittal²,  Dan Schonfeld¹,  Prith Banerjee^3
1University of Illinois at Chicago, ²BINACHIP Inc., ³HP Company

3:02PM
2D.24
Phenomenological Model for Gate Length Bias Dependent Inverter Delay Change with Emphasis on Library Characterization
Qian Ying Tang¹,  Qiang Chen²,  Sridhar Tirumala^2
1UC Berkeley, ²Synopsys

3:06PM
2D.25
Statistical Decoupling Capacitance Allocation By Efficient Numerical Quadrature Method
Thom Jefferson Eguia,  Ning Mi,  Sheldon Tan
University of California Riverside

3:10PM
2D.26
A Novel ACO-based Pattern Generation for Peak Power Estimation in VLSI Circuits
Yi-Ling Liu¹,  Chun-Yao Wang¹,  Yung-Chih Chen¹,  Ya-Hsin Chang^2
1National Tsing Hua University, ²

3:14PM
2D.27
Switch Level Optimization of Digital CMOS Gate Networks
Leomar Rosa Jr.¹,  Felipe Schneider²,  Renato Ribas¹,  Andre Reis^2
1UFRGS, ²Nangate

Chair: José Silva Matos
Co-Chair: Sao-Jie Chen

3:30PM
3A.1
hArtes Design Flow for Heterogeneous Platforms
Muhammad Rashid¹,  Fabrizio Ferrandi²,  Koen Bertels^3
1Thomson R&D France, ²Politecnico di Milano, Dipartimento di Elettronica Informazione, Italy, ³Computer Engineering Department, Delft University, Netherland

4:00PM
3A.2
An Efficient Reliability Evaluation Approach for System-Level Design of Embedded Systems
Adeel Israr,  Abdulhadi Shoufan,  Sorin Huss
TUD

4:20PM
3A.3
A Case Study on System-Level Modeling by Aspect-Oriented Programming
Feng Liu¹,  Otmane Ait Mohamed²,  Xiaoyu Song³,  Qingping Tan^1
1National Lab of Parallel Distributed Processing. Changsha, Hunan, China, ²ECE Dept, Concordia University, Montreal, Quebec, Canada, ³ECE Dept, Portland State University, Portland, USA

4:40PM
3A.4
Performance Evaluation of Wireless Networks on Chip Architectures
Amlan Ganguly¹,  Kevin Chang¹,  Partha Pande¹,  Benjamin Belzer¹,  Alireza Nojeh^2
1Washington State University, ²University of British Columbia

Chair: Smita Krishnaswamy
Co-Chair: Sreejit Chakravarty

3:30PM
3B.1
Tutorial Proposal: Validating Physical Access Layer of WiMAX Using System Verilog
Albert Chiang¹,  Wei-Hua Han¹,  Bhanu Kapoor^2
1Synopsys, ²Mimasic

4:00PM
3B.2
Accelerating Jitter Tolerance Qualification for High Speed Serial Interfaces
Yongquan Fan and Zeljko Zilic
McGill University

4:20PM
3B.3
Improving the Accuracy of Rule-based Equivalence Checking of System-level Design Descriptions by Identifying Potential Internal Equivalences
Hiroaki Yoshida and Masahiro Fujita
University of Tokyo

4:40PM
3B.4
Efficient SAT-Based Techniques for Design of Experiments by Using Static Variable Ordering
Miroslav Velev and Ping Gao
Aries Design Automation

5:00PM
3B.5
An Abstraction Mechanism to maximize stimulus portability across RTL, FPGA, Software models and Silicon of SoCs
Mrinal Bose,  Prashant Naphade,  Jayanta Bhadra,  Hillel Miller
Freescale

Chair: Rajendran Panda
Co-Chair: Jay Sivagnaname

3:30PM
3C.1
Timing Yield Estimation of Digital Circuits using a Control Variate Technique
Javid Jaffari and Mohab Anis
Spry Design Automation & University of Waterloo

4:00PM
3C.2
A Unified Gate Sizing Formulation for Optimizing Soft Error Rate, Cross-talk Noise and Power under Process Variations
Koustav Bhattacharya and Nagarajan Ranganathan
Dept. of CSE, USF

4:20PM
3C.3
TuneLogic: Post-Silicon Tuning of Dual-Vdd Designs
Stephen Bijansky,  Adnan Aziz,  Scott Lee
University of Texas

4:40PM
3C.4
A Case for Exploiting Complex Arithmetic Circuits towards Performance Yield Enhancement
Shingo Watanabe¹,  Masanori Hashimoto²,  Toshinori Sato^3
1Kyushu Institute of Technology, ²Osaka University, ³Fukuoka University

5:00PM
3C.5
A Systematic Approach to Modeling and Analysis of Transient Faults in Logic Circuits
Natasa Miskov-Zivanov
Carnegie Mellon University

Chair: Anand Iyer
Co-Chair: Kamesh Gadepally

3:18PM
3D.1
ESD Event Simulation Automation using Automatic Extraction of the Relevant Portion of a Full Chip
Thorsten Weyl¹,  Dave Clarke¹,  Karl Rinne²,  James A. Power^1
1Analog Devices, ²University of Limerick

3:22PM
3D.2
Simulation-Based Optimal Guard-Ring Design for Reduction of Retention Time Failure Due to Substrate Coupling Noise in High-Density DRAM Cores
Jeong-Yeol Kim,  Ji-Hyun Lee,  Ho-Soon Shin,  Kyung-Ho Lee,  Moon-Hyun Yoo
Memory R&D Center, Samsung Electronics, Korea

3:26PM
3D.3
Parametric Analysis to Determine Accurate Interconnect Extraction Corners for Design Performance
Ayhan Mutlu,  Kelvin Le,  Ruben Molina,  Mustafa Celik
Extreme DA Corporation

3:30PM
3D.4
Exploratory Study on Circuit and Architecture Design of Very High Density Diode-Switch Phase Change Memories
Shu Li and Tong Zhang
Rensselaer Polytechnic Institute

3:34PM
3D.5
A Voltage Controlled Nano Addressing Circuit
Bao Liu
UTSA

3:38PM
3D.6
Defect Characterization in Magnetic Cellular Automata (MCA) Arrays
Anita Kumari,  Javier Pulecio,  Sanjukta Bhanja
University of South Florida

3:42PM
3D.7
CAD Utilities to Comprehend Layout-Dependent Stress Effects in 45 nm High- Performance SOI Custom Macro Design
Akif Sultan,  John Faricelli,  Sushant Suryagandh,  Hans VanMeer,  Kaveri Mathur,  James Pattison,  Sean Hannon,  Greg Constant,  Kalyana Kumar,  Kevin Carrejo,  Joe Meier,  Rasit Topaloglu,  Darin Chan,  Uwe Hahn,  Thorsten Knopp
AMD

3:46PM
3D.8
A 1.2 Volt, 90nm, 16-Bit Three Way Segmented Digital to Analog Converter (DAC) for Low Power Applications
Maruthi Chandrasekhar BH and Sudeb Dasgupta
Indian Institute of Technology, Roorkee

3:50PM
3D.9
Design Methodology of High Performance On-Chip Global Interconnect Using Terminated Transmission-Line
Yulei Zhang¹,  Ling Zhang¹,  Alina Deutsch²,  George Katopis²,  Daniel Dreps²,  James Buckwalter¹,  Ernest Kuh³,  Chung-Kuan Cheng^1
1UCSD, ²IBM, ³UC Berkeley

3:54PM
3D.10
New Word-line Driving Scheme for Suppressing Oxide-Tunneling Leakage in Sub-65-nm SRAMs
Ji-Hye Bong¹,  Yong-Jin Kwon¹,  Kyeong-Sik Min²,  Sung-Mo (Steve) Kang^3
1Kookmin University, ²Kookmin University, UC Merced, ³UC Merced

3:58PM
3D.11
Adaptive Leakage Control on Body Biasing for Reducing Power Consumption in CMOS VLSI Circuit
Xin He,  Syed Al-Kadry,  Afshin Abdollahi
University of California, Riverside

4:02PM
3D.12
Standby power reduction and SRAM cell optimization for 65nm technology
S Lakshminarayanan¹,  Junho Joung¹,  Geetha Narasimhan¹,  Ravi Kapre¹,  Miroslav Slanina¹,  James Tung¹,  Morgan Whately¹,  C.L Hou²,  W.J Liao²,  S.C Lin²,  P-G Ma²,  C-W Fan²,  M-C Hsieh²,  F-C Liu²,  K-L Yeh^2
1Cypress Semiconductor, ²United Microelectronics Corporation

4:06PM
3D.13
Optimization Strategies to Improve Statistical Timing
Parimala Viswanath,  Pranav Murthy,  Debajit Das,  Ramakrishnan Venkatraman,  Ajoy Mandal,  Arvind Veeravalli,  Udayakumar H
Texas Instruments India Ltd.

4:10PM
3D.14
Clock Gating Effectiveness: Applications to Power Optimization
Jithendra Srinivas,  Madhusudan Rao,  Jairam S
SDTC TI India

4:14PM
3D.15
Buffer/Flip-Flop Block Planning for Power-Integrity-Driven Floorplanning
Hsin-Hwa Pan¹,  Hung-Ming Chen²,  Chia-Yi Chang^3
1AnaGlobe Technology, Inc., ²Dept of EE, NCTU, Taiwan, ³Himax Technologies, Inc.

4:18PM
3D.16
On Temperature Planarization Effect of Copper Dummy Fills in Deep Nanometer Technology
Basab Datta and Wayne Burleson
Electrical & Computer Engineering Department, University of Massachusetts-Amherst

4:22PM
3D.17
Fast Characterization of Parameterized Cell Library
Uday Doddannagari¹,  Shiyan Hu²,  Weiping Shi^1
1Texas A&M University, ²Michigan Technology University

4:26PM
3D.18
Cell Shifting Aware of Wirelength and Congestion
Liu Dawei
Tsinghua University

4:30PM
3D.19
Lagrangian Relaxation Based Register Placement for High-Performance Circuits
Mei-Fang Chiang¹,  Takumi Okamoto²,  Takeshi Yoshimura^1
1Waseda University, ²NEC

4:34PM
3D.20
Implementation of Power Managed Hyper Transport System for Transmission of HD Video
Adithya V. Kodati,  Koneswara S. Vemuri,  Lili He,  Morris Jones
San Jose State University

4:38PM
3D.21
Power Aware Placement for FPGAs with Dual Supply Voltages
Zohreh Karimi and Majid Sarrafzadeh
UCLA

4:42PM
3D.22
VLSI Architectures of Perceptual Based Video Watermarking for Real-Time Copyright Protection
Saraju Mohanty,  Elias Kougianos,  Manish Ratnani
University of North Texas

4:46PM
3D.23
VeriC: A Semi-Hardware Description Language to Bridge the Gap Between ESL Design and RTL Models
Shu-Hsuan Chou,  Che-Neng Wen,  Yan-Ling Liu,  Tien-Fu Chen
National Chung Cheng University

4:50PM
3D.24
Power Estimation Methodology for a High-Level Synthesis Framework
Sumit Ahuja¹,  Deepak A Mathaikutty²,  Gaurav Singh²,  Joe Stetzer²,  Sandeep Shukla²,  Ajit Dingankar^2
1FERMAT Lab, Virginia Tech., ²

4:54PM
3D.25
Variability Aware Modeling of SoCs: from device variations to manufactured system yield
Miguel Miranda¹,  Dierickx Bart¹,  Zuber Paul¹,  Dobrovolny Petr¹,  Kutscherauer Florian²,  Roussel Philippe^1
1IMEC, ²Univ. Hagenberg

4:58PM
3D.26
Kriging Model Combined with Latin Hypercube Sampling for Surrogate Modeling of Analog Integrated Circuit Performance
Hailong You,  Maofeng Yang,  Xinzhang Jia,  Dan Wang
Key Lab of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi'an, China

Chair: Kamesh Gadepally
Co-Chair: Lalitha Immaneni

10:30AM
4A.1
Invited (IC Packaging Co-Design)
Joseph Fjelstad
Verdant Electronics

11:40AM
4A.2
Invited (IC Packaging and Co-Design)
Farhang Yazdani
BroadPak

11:00AM
4A.3
Die/Wafer Stacking with Reciprocal Design Symmetry (RDS) for Mask Reuse in Three-dimensional (3D) Integration Technology
Syed M. Alam¹,  Robert E. Jones²,  Scott Pozder²,  Ankur Jain^2
1EverSpin Technologies, Inc., ²Freescale Semiconductor

11:20AM
4A.4
Parallel flow to analyze the impact of the voltage regulator model in nanscale power distribution network
Amirali Shayan,  Xiang Hu,  He Peng,  Wanping Zhang,  Chung-Kuan Cheng
University of California San Diego

Chair: Anand Iyer
Co-Chair: Shankar Hemmady

10:30AM
4B.1
An Analytic Model for Ge/Si Core/Shell Nanowire MOSFETs Considering Drift-Diffusion and Ballistic Transport
Lining Zhang,  Jin He,  Jian Zhang,  Feng Liu,  Yue Fu,  Xing Zhang
IME, Peking University

11:00AM
4B.2
Zero Clock Skew Synchronization With Rotary Clocking Technology
Vinayak Honkote and Baris Taskin
Drexel University

11:20AM
4B.3
Place and Route Considerations for Voltage Interpolated Designs
Kevin Brownell,  A. Durlov Khan,  David Brooks,  Gu-Yeon Wei
Harvard University

11:40AM
4B.4
Crosstalk Pessimism Reduction with Path Based Analysis
Genichi Tanaka and Koichi Nakashiro
Renesas Technology Corp.

Chair: Jay Sivagnaname
Co-Chair: Valeriy Sukharev

10:30AM
4C.1
The Impact of BEOL Lithography Effects on the SRAM Cell Performance and Yield
Ying Zhou¹,  Rouwaida Kanj²,  Kanak Agarwal²,  Zhuo Li²,  R. Joshi³, Sani Nassif²,  Weiping Shi^1
1Texas A&M University, ²IBM Austin Research Lab, ³IBM TJ Watson Labs

11:00AM
4C.2
Process Variation Impact on FPGA Configuration Memory
Yanzhong Xu,  Lin-Shih Liu,  Mark Chan,  Jeff Watt
Altera Corporation

11:20AM
4C.3
Efficient Statistical Analysis of Read Timing Failures in SRAM Circuits
SONER YALDIZ,  UMUT ARSLAN,  XIN LI,  LARRY PILEGGI
Carnegie Mellon University

11:40AM
4C.4
Increasing Memory Yield in Future Technologies through Innovative Design
Costas Argyrides¹,  Ahmad Al-Yamani²,  Carlos Lisboa³,  Luigi Carro³,  Dhiraj Pradhan^1
1Department of Computer Science, University of Bristol, UK, ²Department of Computer Engineering, KFUPM, SA, ³Instituto de Informatica, PPGC, UFRGS, Brazil

Chair: Miroslav Velev
Co-Chair: Rasit Topaloglu

1:30PM
5A.1
An Efficient Current-Based Logic Cell Model for Crosstalk Delay Analysis
Debasish Das¹,  William Scott²,  Shahin Nazarian²,  Hai Zhou^1
1Northwestern University, ²Magma Design Automation

2:00PM
5A.2
An Application-Specific Adjoint Sensitivity Analysis Framework for Clock Mesh Sensitivity Computation
Xiaoji Ye and Peng Li
Department of ECE, Texas A&M University

2:30PM
5A.3
Early Clock Prototyping for Design Analysis and Quality Entitlement
Ramamurthy Vishweshwara,  Ramakrishnan Venkatraman,  Vipul Kadodwala
Texas Instruments India

2:50PM
5A.4
Automatic Register Banking for Low-Power Clock Trees
Wenting Hou and Pei-Hsin Ho
Synopsys Inc.

3:10PM
5A.5
A Study of Decoupling Capacitor Effectiveness in Power and Ground Grid Networks
Aida Todri¹,  Malgorzata Marek-Sadowska¹,  Francois Maire²,  Christophe Matheron^2
1UCSB, ²STMicroelectronics

Chair: Mark Budnik
Co-Chair: Saraju Mohanty

1:30PM
5B.1
A Half-Selection Free 10T SRAM Cell Using Column Lines Assist (CLA) Scheme
Shunsuke Okumura¹,  Yusuke Iguchi¹,  Shusuke Yoshimoto¹,  Hidehiro Fujiwara¹,  Hiroki Noguchi¹,  Koji Nii²,  Hiroshi Kawaguchi¹,  Masahiko Yoshimoto^1
1Kobe University, ²Renesas Technology

2:00PM
5B.2
Design and Implementation of a Sub-threshold BFSK Transmitter
Suganth Paul¹,  Rajesh Garg²,  Sunil Khatri²,  Sheila Vaidya^3
1Intel Corportation, ²Texas A&M University, ³Lawrence Livermore National Laboratory

2:30PM
5B.3
A Universal Level Converter Towards the Realization of Energy Efficient Implantable Drug Delivery Nano-Electro-Mechanical-Systems
Saraju Mohanty¹,  Dhruva Ghai¹,  Elias Kougianos¹,  Bharat Joshi^2
1University of North Texas, ²University of North Carolina at Charlotte

2:50PM
5B.4
Temperature Effects on Energy Optimization in Sub-Threshold Circuit Design
Basab Datta and Wayne Burleson
Electrical & Computer Engineering Department, University of Massachusetts-Amherst

3:10PM
5B.5
Charge Recovery Logic as a Side Channel Attack Countermeasure
Amir Moradi,  Mehrdad Khatir,  Mahmoud Salmasizadeh,  Mohammad-T. Manzuri Shalmani
Sharif University of Technology, Tehran, Iran

Chair: Bhadra Jay
Co-Chair: Alberto Bosio

1:30PM
5C.1
Tutorial Proposal: Impact of SoC Power Management Techniques on Verification and Testing
Bhanu Kapoor¹,  Shankar Hemmady²,  Shireesh Verma³,  Kaushik Roy⁴,  Manuel D'Abreu^5
1Mimasic, ²Synopsys, ³Conexant, ⁴Purdue University, ⁵Sandisk Corp

2:00PM
5C.2
A Study on Impact of Loading Effect on Capacitive Crosstalk Noise
Alodeep Sanyal,  Abhisek Pan,  Sandip Kundu
ECE Department, University of Massachusetts at Amherst

2:30PM
5C.3
Simultaneous Test Pattern Compaction, Ordering and X-Filling for Testing Power Reduction
Ju-Yueh Lee¹,  Yu Hu¹,  Rupak Majumdar²,  Lei He^1
1Electrical Engineering Department, UCLA, ²Computer Science Department, UCLA

2:50PM
5C.4
Markov Source Based Test Length Optimized SCAN-BIST architecture
Aftab Farooqi¹,  Sudhakar Reddy²,  Chris Monico^1
1Texas Tech University, ²University of Iowa

3:10PM
5C.5
Calculation of Stress Probability for NBTI-Aware Timing Analysis
Alexander Stempkovsky,  Alexey Glebov,  Sergey Gavrilov
Research Institute for Design Problems in Microelectronics (IPPM RAS)

Chair: José Silva Matos
Co-Chair: Rasit Topaloglu

3:45PM
6A.1
Derating for Static Timing Analysis: Theory and Practice
Ali Dasdan¹,  Santanu Kolay¹,  Mustafa Yazgan^2
1Yahoo! Inc., ²Extreme DA Inc.

4:15PM
6A.2
An Information Theoretic Framework to Compute the MAX/MIN Operations in Parameterized Statistical Timing Analysis
Nikolay Rubanov
Cadence Design Systems

4:45PM
6A.3
A Generalized V-shaped Multi-level Method for Large Scale Floorplanning
Song Chen,  Zheng Xu,  Takeshi Yoshimura
Waseda University

5:05PM
6A.4
Simultaneous Buffer and Interlayer Via Planning for 3D Floorplanning
Xu He,  Sheqin Dong,  Yuchun Ma,  Xianlong Hong
tsinghua university

5:25PM
6A.5
IR-Drop Management CAD Techniques in FPGAs for Power Grid Reliability
Akhilesh Kumar and Mohab Anis
University of Waterloo

Chair: Sheldon Tan
Co-Chair: Hao Yu

3:45PM
6B.1
Functionally Valid Gate-level Peak Power Estimation for Processors
Sriram Sambamurthy,  Sankar Gurumurthy,  Ramtilak Vemu,  Jacob A. Abraham
University of Texas at Austin

4:15PM
6B.2
On-Chip DC-DC Converters for Three-Dimensional ICs
Jonathan Rosenfeld and Eby Friedman
University of Rochester

4:45PM
6B.3
Active Decap Design Considerations for Optimal Supply Noise Reduction
Xiongfei Meng and Resve Saleh
University of British Columbia

5:05PM
6B.4
Efficient Power Network Analysis with Complete Inductive Modeling
Shan Zeng¹,  Wenjian Yu¹,  Wanping Zhang²,  Jian Wang¹,  Xianlong Hong¹,  Chung-Kuan Cheng^2
1EDA Lab, Dept. Computer Science & Technology, Tsinghua University, Beijing 100084, P.R. China, ²Department of Computer Science and Engineering, University of California, San Diego, CA 92093, USA

5:25PM
6B.5
Parallel Partitioning Based On-Chip Power Distribution Network Analysis Using Locality Acceleration
Zhiyu Zeng,  Peng Li,  Zhuo Feng
Texas A&M University

Chair: Keith Bowman
Co-Chair: Hamid Mahmoodi

3:45PM
6C.1
SRAM supply voltage scaling: a reliability perspective
Animesh Kumar,  Jan Rabaey,  Kannan Ramchandran
University of California, Berkeley

4:15PM
6C.2
Low Power Adaptive Pipeline Based on Instruction Isolation
Seung Eun Lee¹,  Chris Wilkerson²,  Ming Zhang²,  Rajendra Yavatkar²,  Shih-Lien L. Lu²,  Nader Bagherzadeh^1
1University of California, Irvine, ²Intel Corporation

4:45PM
6C.3
Post-Silicon Clock-Invert (PSCI) for Reducing Process-Variation Induced Skew in Buffered Clock Networks
Charbel Akl¹,  Rafic Ayoubi²,  Magdy Bayoumi^1
1University of Louisiana at Lafayette, ²University of Balamand

5:05PM
6C.4
Variation-Tolerant Hierarchical Voltage Monitoring Circuit for Soft Error Detection
Ashay Narsale and Michael Huang
University of Rochester

5:25PM
6C.5
SEU Hardened Clock Regeneration Circuits
Rajballav Dash,  Rajesh Garg,  Sunil Khatri,  Gwan Choi
Texas A&M University

Chair: Lech Józwiak
Co-Chair: Artur Chojnacki

3:45PM
6D.1
PVT Variation Impact on Voltage Island Formation in MPSoC Design
Sohaib Majzoub¹,  Resve Saleh¹,  Rabab Ward^2
1SoC Research Lab, Department of Electrical and Computer Engineering, University of British Columbia, ²Image Processing Lab, Department of Electrical & Computer Engineering, University of British Columbia

4:15PM
6D.2
Uncriticality-directed Scheduling for Tackling Variation and Power Challenges
Toshinori Sato¹ and Shingo Watanabe^2
1Fukuoka University, ²Kyushu Institute of Technology

4:45PM
6D.3
Energy-Efficient Router Buffers with Bypassing for Network-on-Chips (NoCs)
Avinash Kodi¹,  Ahmed Louri²,  Janet Wang^2
1Ohio University, ²University of Arizona

5:05PM
6D.4
NBTI Aware Workload Balancing in Multi-core Systems
Jin Sun¹,  Avinash Kodi²,  Ahmed Louri¹,  Janet Wang^1
1Univ. of Arizona, ²Ohio University

5:25PM
6D.5
Joint Write Policy and Fault-Tolerance Mechanism Selection for Caches in DSM Technologies: Energy-Reliability Trade-off
Mehrtash Manoochehri, Alireza Ejlali, Seyed Ghassem Miremadi
Department of Computer Engineering, Sharif University of Technology