Statistical static timing analysis (SSTA) has been used in practice as an extension to regular static timing analysis (STA) to analyse for the impact of process variations on timing in new process nodes. However, the use of statistical timing in design optimization is a challenge that chip design teams face. In this paper, we propose some approaches to enable the comprehension of statistical timing behaviour during optimization. We indicate how the design standard-cell library can be analysed for variation, to help in understanding the robustness of cells, and in enabling the use of the correct logic architectures. We then propose an approach to comprehend the statistical timing behaviour in conventional (static-timing-based) optimization engines. We show how this method helps in optimising the overall area of the design, while simultaneously improving the timing characteristics. We also indicate a complementary approach of incrementally optimising the design using the statistical characteristics of the library as an added cost for sizing. We show how these approaches resulted in a 9.1% reduction in design area, and a direct improvement in statistical timing of a complex real-life design.