Current comparators are important building blocks within many analogue circuit designs. In particular, they are used for front-end signal processing applications and increasingly within neuromorphic electronic systems. Low voltage and low power application demands confront voltage mode IC designs, for there is less dynamic available under low power supply condition. While the circuit implemented in current mode technique occupies small area, consumes less power dissipation and achieves more dynamic range and high operation speed. Thus the current mode circuit design methodology receives increasing wide attention in the recent years. Moreover, many sensors in SoC such as temperature sensors, photo sensors provide current signal. In these applications and high speed data converters, where the function of comparison is a limiting component for accuracy, noise and power consumption reasons, the introduction of current mode solutions is highly desirable. The current comparison process is injecting one or two current flowing into the comparator and distinguishing the current (or the difference of two currents) is positive or negative. The output voltage generated by the output current is used conveniently to indicate the result of the comparison. The comparison process is relatively simple, but the implementation of the current comparator is becoming more complex. Low input impedance, which is required by current mode circuits, should be considered first. Secondly, a quick time response is demanded by the current comparator. The main limitation to the time response usually comes from the initial balance of the output branches that often leads to the triode region some output transistors. Finally, the precision of comparator designs are playing an important role in the design requirements, and it depends on the offset caused by the mismatch of transistors. In the recent years, there have been many good implementations reported. However, many of the proposed implementations had only emphasized on one or several aspects at the cost of deterioration in other characteristics. In this paper we present an ultra high speed low current comparator with low input impedance using a simple biasing method. It is optimized for low power consumption whilst maintaining high speed. This novel approach in comparator design offers a reduction in power consumption compared with other high speed designs. The simulation results demonstrate the propagation delay is about 0.7 nsec and the average power consumption is 107 μW for 100 nA input current at supply voltage of 1.8 V using 0.35 μm CMOS technology.