Multiple supply voltage (MSV) is an effective method to optimize the chip power consumption. In MSV design, the voltage island is a crucial concern that the blocks with the same voltage level are clustered into one or more voltage islands to reduce the costs of voltage supply network and level converter. The distribution of voltage islands depends on not only the feasible voltage assignment based on timing analysis, but also the physical adjacency between blocks. In traditional post-floorplan voltage island generation approaches, the fixed layout of blocks limits the power optimization greatly. Instead of a start-over searching process to generate better solutions, which suffers from long run time and poor scalability, in this paper, we propose an incremental power optimization methodology to further optimize the power consumption of traditional post-floorplan MSV design without compromising the circuit performance. A net-flow based timing slack distribution algorithm is proposed to obtain maximal power reduction, considering both the characters of each block and the circuit topology. Then we incrementally change the floorplan to re-construct the voltage island distribution based on the physical constraint graph, while the chip area, the total wire length and the per-formance are considered simultaneously. The experimental results show that our methodology can reduce the power consumption while the chip area, the total wire length and the power supply network cost are main-tained at the same time.