As the technology scaled down, it is known that interconnect has become the dominant factor in determining the overall circuit performance and complexity. Buffer insertion is one of very effective and useful techniques to improve the interconnect performance. In order to find better places for buffers to be inserted, the buffer insertion stage during floorplanning usually clusters buffers in a region, which may cause additional IR-drop violation. On the other hand, in complex digital system with relatively large die areas operating at very high frequencies, many global signals traveling across the chip need several clock cycles to reach their destinations, thus requiring the adoption of pipelined interconnects. Together with the buffer stations/blocks, the increasing number of flip-flops will cause further voltage drop violation. In this paper, we propose a methodology to pipeline interconnect during the floorplan stage and consider the IR-drop during the planning of buffers and flip-flops at the same time. The experimental results show that our method can get a low system latency with power integrity preservation in 90nm technology node.