Power dissipation is an important consideration in VLSI circuits. This paper emphasizes the adaptive leakage control on body bias technique to reduce the power dissipation of the 65 nm MOS devices. Through adding forward body biasing, the leakage is reduced in sub-100 nm CMOS devices (unlike above-100 nm devices) while slightly increasing the signal propagation delay. For the conditions where the circuit does not use up the entire clock cycle, this slack can be used to reduce the power dissipation without any loss in performance. The fact that the circuit delay remains less than the clock period provides the opportunity to reduce power consumption of VLSI circuits. The objective is to change the voltage of the body bias to reduce leakage, allowing the circuit to consume less power whenever the clock edge can be met as detected beforehand.