This paper presents a power-gating structure that employs a staggered-phase damping technique for suppressing power and ground rails fluctuation and stabilization time during mode-transition. Two same type sleep devices coupled to two clusters in a single power domain are switched-on at different time instants such that the turn-on time of one of these is delayed by half the resonant oscillation period relative to the turn-on time of the other. The same can be generalized to plurality of clusters where one set of sleep devices switch at the first time instant and the other set switch at the said second time instant. This technique was evaluated in a 1-V 90-nm CMOS technology in the context of a 3-stage 16-bit Carry-Select-Adder (CSA) component, and also compared to the parallel sleep transistor technique that is based on reducing the instantaneous excitation current. Results show that the present technique reduces peak noise by 33.2% compared to standard power-gating structure, and achieves a settling time reduction of 4.03× and 3.21× compared to standard and parallel sleep transistor power-gating structures, respectively.