Today’s process technologies place emphasis on low power design in multi-core systems that require the complicate communication networks-on-chip (NoC) architecture to be reliable. Considering the many error control codes (ECCs) implemented in a hardware NoC router, the primary objective of this paper is accounting for the causes of energy consumed for fault tolerance and providing a way of comparison among different ECC methods. To make a proper choice, tradeoff between power and throughput of each ECC achieving the same reliability must be considered. Hence, some low-overhead ECC methods used in NoC have been implemented in hardware and their performance-energy tradeoff shown.